Add vsrlr/vsrar

README.md

@@ -6,10 +6,6 @@ Arranged from QEMU implementation and [GCC Intrinsics](https://gcc.gnu.org/onlin
 
 TODO List:
 
-### vsrlr.b/h/w/d
-
-### vsrar.b/h/w/d
-
 ### vsrln.b.h/h.w/w.d
 
 ### vsran.b.h/h.w/w.d

code/gen_impl.py

@@ -379,6 +379,34 @@
             file=f,
         )
         print(f"}}", file=f)
+    with open(f"vsrlr_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(f"  if ((b.{m}[i] & 0x{w-1:x}) == 0) {{", file=f)
+        print(
+            f"    dst.{m}[i] = a.{m}[i];",
+            file=f,
+        )
+        print(f"  }} else {{", file=f)
+        print(
+            f"    dst.{m}[i] = (a.{m}[i] >> (b.{m}[i] & 0x{w-1:x})) + ((a.{m}[i] >> ((b.{m}[i] & 0x{w-1:x}) - 1)) & 0x1);",
+            file=f,
+        )
+        print(f"  }}", file=f)
+        print(f"}}", file=f)
+    with open(f"vsrar_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(f"  if ((b.{m}[i] & 0x{w-1:x}) == 0) {{", file=f)
+        print(
+            f"    dst.{m}[i] = a.{m}[i];",
+            file=f,
+        )
+        print(f"  }} else {{", file=f)
+        print(
+            f"    dst.{m}[i] = ((s{w})a.{m}[i] >> (b.{m}[i] & 0x{w-1:x})) + (((s{w})a.{m}[i] >> ((b.{m}[i] & 0x{w-1:x}) - 1)) & 0x1);",
+            file=f,
+        )
+        print(f"  }}", file=f)
+        print(f"}}", file=f)
 
 for width in ["s", "d"]:
     m = members_fp[width]

code/gen_tb.py

@@ -83,7 +83,9 @@
     "vslt": (widths_all, "v128 a, v128 b"),
     "vsle": (widths_all, "v128 a, v128 b"),
     "vsrl": (widths_signed, "v128 a, v128 b"),
+    "vsrlr": (widths_signed, "v128 a, v128 b"),
     "vsra": (widths_signed, "v128 a, v128 b"),
+    "vsrar": (widths_signed, "v128 a, v128 b"),
     "vsub": (widths_signed, "v128 a, v128 b"),
     "vsubwev": (widths_vsubw, "v128 a, v128 b"),
     "vsubwod": (widths_vsubw, "v128 a, v128 b"),

code/vsrar_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrar_b(v128 a, v128 b) {
+  v128 dst;
+#include "vsrar_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrar_b); }

code/vsrar_b.h

@@ -0,0 +1,8 @@
+for (int i = 0; i < 16; i++) {
+  if ((b.byte[i] & 0x7) == 0) {
+    dst.byte[i] = a.byte[i];
+  } else {
+    dst.byte[i] = ((s8)a.byte[i] >> (b.byte[i] & 0x7)) +
+                  (((s8)a.byte[i] >> ((b.byte[i] & 0x7) - 1)) & 0x1);
+  }
+}

code/vsrar_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrar_d(v128 a, v128 b) {
+  v128 dst;
+#include "vsrar_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrar_d); }

code/vsrar_d.h

@@ -0,0 +1,8 @@
+for (int i = 0; i < 2; i++) {
+  if ((b.dword[i] & 0x3f) == 0) {
+    dst.dword[i] = a.dword[i];
+  } else {
+    dst.dword[i] = ((s64)a.dword[i] >> (b.dword[i] & 0x3f)) +
+                   (((s64)a.dword[i] >> ((b.dword[i] & 0x3f) - 1)) & 0x1);
+  }
+}

code/vsrar_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrar_h(v128 a, v128 b) {
+  v128 dst;
+#include "vsrar_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrar_h); }

code/vsrar_h.h

@@ -0,0 +1,8 @@
+for (int i = 0; i < 8; i++) {
+  if ((b.half[i] & 0xf) == 0) {
+    dst.half[i] = a.half[i];
+  } else {
+    dst.half[i] = ((s16)a.half[i] >> (b.half[i] & 0xf)) +
+                  (((s16)a.half[i] >> ((b.half[i] & 0xf) - 1)) & 0x1);
+  }
+}

code/vsrar_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrar_w(v128 a, v128 b) {
+  v128 dst;
+#include "vsrar_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrar_w); }

code/vsrar_w.h

@@ -0,0 +1,8 @@
+for (int i = 0; i < 4; i++) {
+  if ((b.word[i] & 0x1f) == 0) {
+    dst.word[i] = a.word[i];
+  } else {
+    dst.word[i] = ((s32)a.word[i] >> (b.word[i] & 0x1f)) +
+                  (((s32)a.word[i] >> ((b.word[i] & 0x1f) - 1)) & 0x1);
+  }
+}

code/vsrlr_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrlr_b(v128 a, v128 b) {
+  v128 dst;
+#include "vsrlr_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrlr_b); }

code/vsrlr_b.h

@@ -0,0 +1,8 @@
+for (int i = 0; i < 16; i++) {
+  if ((b.byte[i] & 0x7) == 0) {
+    dst.byte[i] = a.byte[i];
+  } else {
+    dst.byte[i] = (a.byte[i] >> (b.byte[i] & 0x7)) +
+                  ((a.byte[i] >> ((b.byte[i] & 0x7) - 1)) & 0x1);
+  }
+}

code/vsrlr_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrlr_d(v128 a, v128 b) {
+  v128 dst;
+#include "vsrlr_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrlr_d); }

code/vsrlr_d.h

@@ -0,0 +1,8 @@
+for (int i = 0; i < 2; i++) {
+  if ((b.dword[i] & 0x3f) == 0) {
+    dst.dword[i] = a.dword[i];
+  } else {
+    dst.dword[i] = (a.dword[i] >> (b.dword[i] & 0x3f)) +
+                   ((a.dword[i] >> ((b.dword[i] & 0x3f) - 1)) & 0x1);
+  }
+}

code/vsrlr_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrlr_h(v128 a, v128 b) {
+  v128 dst;
+#include "vsrlr_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrlr_h); }

code/vsrlr_h.h

@@ -0,0 +1,8 @@
+for (int i = 0; i < 8; i++) {
+  if ((b.half[i] & 0xf) == 0) {
+    dst.half[i] = a.half[i];
+  } else {
+    dst.half[i] = (a.half[i] >> (b.half[i] & 0xf)) +
+                  ((a.half[i] >> ((b.half[i] & 0xf) - 1)) & 0x1);
+  }
+}

code/vsrlr_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrlr_w(v128 a, v128 b) {
+  v128 dst;
+#include "vsrlr_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrlr_w); }

code/vsrlr_w.h

@@ -0,0 +1,8 @@
+for (int i = 0; i < 4; i++) {
+  if ((b.word[i] & 0x1f) == 0) {
+    dst.word[i] = a.word[i];
+  } else {
+    dst.word[i] = (a.word[i] >> (b.word[i] & 0x1f)) +
+                  ((a.word[i] >> ((b.word[i] & 0x1f) - 1)) & 0x1);
+  }
+}

docs/lsx/shift.md

@@ -52,11 +52,21 @@ Compute 128-bit `a` shifted right by `imm * 8` bits.
 {{ vsrl('w') }}
 {{ vsrl('d') }}
 
+{{ vsrlr('b') }}
+{{ vsrlr('h') }}
+{{ vsrlr('w') }}
+{{ vsrlr('d') }}
+
 {{ vsra('b') }}
 {{ vsra('h') }}
 {{ vsra('w') }}
 {{ vsra('d') }}
 
+{{ vsrar('b') }}
+{{ vsrar('h') }}
+{{ vsrar('w') }}
+{{ vsrar('d') }}
+
 {{ vrotr('b') }}
 {{ vrotr('h') }}
 {{ vrotr('w') }}

main.py

@@ -677,4 +677,24 @@ def vrotr(name):
             intrinsic=f"__m128i __lsx_vrotr_{name} (__m128i a, __m128i b)",
             instr=f"vrotr.{name} vr, vr, vr",
             desc=f"Rotate right the unsigned {width}-bit elements in `a` by elements in `b`, store the result to `dst`.",
+        )
+
+    @env.macro
+    def vsrlr(name):
+        width = widths[name]
+        signedness = signednesses[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsrlr_{name} (__m128i a, __m128i b)",
+            instr=f"vsrlr.{name} vr, vr, vr",
+            desc=f"Logical right shift (with rounding) the unsigned {width}-bit elements in `a` by elements in `b`, store the result to `dst`.",
+        )
+
+    @env.macro
+    def vsrar(name):
+        width = widths[name]
+        signedness = signednesses[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsrar_{name} (__m128i a, __m128i b)",
+            instr=f"vsrar.{name} vr, vr, vr",
+            desc=f"Arithmetic right shift (with rounding) the signed {width}-bit elements in `a` by elements in `b`, store the result to `dst`.",
         )