Add vsrlrn/vsrarn

README.md

@@ -6,10 +6,6 @@ Arranged from QEMU implementation and [GCC Intrinsics](https://gcc.gnu.org/onlin
 
 TODO List:
 
-### vsrlrn.b.h/h.w/w.d
-
-### vsrarn.b.h/h.w/w.d
-
 ### vssrln.b.h/h.w/w.d
 
 ### vssran.b.h/h.w/w.d

code/gen_impl.py

@@ -113,7 +113,7 @@
             file=f,
         )
         print(f"}}", file=f)
-    if "width" != "q":
+    if width != "d":
         with open(f"vsllwil_{double_width}_{width}.h", "w") as f:
             print(f"for (int i = 0;i < {128 // double_w};i++) {{", file=f)
             print(
@@ -129,13 +129,51 @@
                     file=f,
                 )
                 print(f"}}", file=f)
+            with open(f"vsrlrn_{width}_{double_width}.h", "w") as f:
+                print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+                print(f"if (i < {64 // w}) {{", file=f)
+                print(f"u8 shift = (b.{double_m}[i] & {double_w-1});", file=f)
+                print(f"if (shift == 0) {{", file=f)
+                print(
+                    f"  dst.{m}[i] = (u{w})(u{double_w})a.{double_m}[i];",
+                    file=f,
+                )
+                print(f"}} else {{", file=f)
+                print(
+                    f"  dst.{m}[i] = (u{w})(((u{double_w})a.{double_m}[i] >> shift) + (((u{double_w})a.{double_m}[i] >> (shift - 1)) & 0x1));",
+                    file=f,
+                )
+                print(f"}}", file=f)
+                print(f"}} else {{", file=f)
+                print(f"  dst.{m}[i] = 0;", file=f)
+                print(f"}}", file=f)
+                print(f"}}", file=f)
             with open(f"vsran_{width}_{double_width}.h", "w") as f:
                 print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
                 print(
                     f"  dst.{m}[i] = (i < {64 // w}) ? (s{w})((s{double_w})a.{double_m}[i] >> (b.{double_m}[i] & {double_w-1})) : 0;",
                     file=f,
                 )
                 print(f"}}", file=f)
+            with open(f"vsrarn_{width}_{double_width}.h", "w") as f:
+                print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+                print(f"if (i < {64 // w}) {{", file=f)
+                print(f"u8 shift = (b.{double_m}[i] & {double_w-1});", file=f)
+                print(f"if (shift == 0) {{", file=f)
+                print(
+                    f"  dst.{m}[i] = (s{w})(s{double_w})a.{double_m}[i];",
+                    file=f,
+                )
+                print(f"}} else {{", file=f)
+                print(
+                    f"  dst.{m}[i] = (s{w})(((s{double_w})a.{double_m}[i] >> shift) + (((s{double_w})a.{double_m}[i] >> (shift - 1)) & 0x1));",
+                    file=f,
+                )
+                print(f"}}", file=f)
+                print(f"}} else {{", file=f)
+                print(f"  dst.{m}[i] = 0;", file=f)
+                print(f"}}", file=f)
+                print(f"}}", file=f)
     if sign == "s":
         with open(f"vsrlni_{width}_{double_width}.h", "w") as f:
             print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)

code/gen_tb.py

@@ -115,12 +115,14 @@
     "vsrani": (widths_vsrlni, "v128 a, v128 b, int imm", [0, 7]),
     "vsrar": (widths_signed, "v128 a, v128 b"),
     "vsrari": (widths_signed, "v128 a, int imm", [0, 7]),
+    "vsrarn": (widths_vsrln, "v128 a, v128 b"),
     "vsrl": (widths_signed, "v128 a, v128 b"),
     "vsrli": (widths_signed, "v128 a, int imm", [0, 7]),
     "vsrln": (widths_vsrln, "v128 a, v128 b"),
     "vsrlni": (widths_vsrlni, "v128 a, v128 b, int imm", [0, 7]),
     "vsrlr": (widths_signed, "v128 a, v128 b"),
     "vsrlri": (widths_signed, "v128 a, int imm", [0, 7]),
+    "vsrlrn": (widths_vsrln, "v128 a, v128 b"),
     "vsub": (widths_signed, "v128 a, v128 b"),
     "vsubwev": (widths_vsubw, "v128 a, v128 b"),
     "vsubwod": (widths_vsubw, "v128 a, v128 b"),

code/vsrarn_b_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrarn_b_h(v128 a, v128 b) {
+  v128 dst;
+#include "vsrarn_b_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrarn_b_h); }

code/vsrarn_b_h.h

@@ -0,0 +1,13 @@
+for (int i = 0; i < 16; i++) {
+  if (i < 8) {
+    u8 shift = (b.half[i] & 15);
+    if (shift == 0) {
+      dst.byte[i] = (s8)(s16)a.half[i];
+    } else {
+      dst.byte[i] = (s8)(((s16)a.half[i] >> shift) +
+                         (((s16)a.half[i] >> (shift - 1)) & 0x1));
+    }
+  } else {
+    dst.byte[i] = 0;
+  }
+}

code/vsrarn_h_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrarn_h_w(v128 a, v128 b) {
+  v128 dst;
+#include "vsrarn_h_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrarn_h_w); }

code/vsrarn_h_w.h

@@ -0,0 +1,13 @@
+for (int i = 0; i < 8; i++) {
+  if (i < 4) {
+    u8 shift = (b.word[i] & 31);
+    if (shift == 0) {
+      dst.half[i] = (s16)(s32)a.word[i];
+    } else {
+      dst.half[i] = (s16)(((s32)a.word[i] >> shift) +
+                          (((s32)a.word[i] >> (shift - 1)) & 0x1));
+    }
+  } else {
+    dst.half[i] = 0;
+  }
+}

code/vsrarn_w_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrarn_w_d(v128 a, v128 b) {
+  v128 dst;
+#include "vsrarn_w_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrarn_w_d); }

code/vsrarn_w_d.h

@@ -0,0 +1,13 @@
+for (int i = 0; i < 4; i++) {
+  if (i < 2) {
+    u8 shift = (b.dword[i] & 63);
+    if (shift == 0) {
+      dst.word[i] = (s32)(s64)a.dword[i];
+    } else {
+      dst.word[i] = (s32)(((s64)a.dword[i] >> shift) +
+                          (((s64)a.dword[i] >> (shift - 1)) & 0x1));
+    }
+  } else {
+    dst.word[i] = 0;
+  }
+}

code/vsrlrn_b_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrlrn_b_h(v128 a, v128 b) {
+  v128 dst;
+#include "vsrlrn_b_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrlrn_b_h); }

code/vsrlrn_b_h.h

@@ -0,0 +1,13 @@
+for (int i = 0; i < 16; i++) {
+  if (i < 8) {
+    u8 shift = (b.half[i] & 15);
+    if (shift == 0) {
+      dst.byte[i] = (u8)(u16)a.half[i];
+    } else {
+      dst.byte[i] = (u8)(((u16)a.half[i] >> shift) +
+                         (((u16)a.half[i] >> (shift - 1)) & 0x1));
+    }
+  } else {
+    dst.byte[i] = 0;
+  }
+}

code/vsrlrn_h_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrlrn_h_w(v128 a, v128 b) {
+  v128 dst;
+#include "vsrlrn_h_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrlrn_h_w); }

code/vsrlrn_h_w.h

@@ -0,0 +1,13 @@
+for (int i = 0; i < 8; i++) {
+  if (i < 4) {
+    u8 shift = (b.word[i] & 31);
+    if (shift == 0) {
+      dst.half[i] = (u16)(u32)a.word[i];
+    } else {
+      dst.half[i] = (u16)(((u32)a.word[i] >> shift) +
+                          (((u32)a.word[i] >> (shift - 1)) & 0x1));
+    }
+  } else {
+    dst.half[i] = 0;
+  }
+}

code/vsrlrn_w_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrlrn_w_d(v128 a, v128 b) {
+  v128 dst;
+#include "vsrlrn_w_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrlrn_w_d); }

code/vsrlrn_w_d.h

@@ -0,0 +1,13 @@
+for (int i = 0; i < 4; i++) {
+  if (i < 2) {
+    u8 shift = (b.dword[i] & 63);
+    if (shift == 0) {
+      dst.word[i] = (u32)(u64)a.dword[i];
+    } else {
+      dst.word[i] = (u32)(((u64)a.dword[i] >> shift) +
+                          (((u64)a.dword[i] >> (shift - 1)) & 0x1));
+    }
+  } else {
+    dst.word[i] = 0;
+  }
+}

docs/lsx/shift.md

@@ -88,6 +88,9 @@ Compute 128-bit `a` shifted right by `imm * 8` bits.
 {{ vsrari('w') }}
 {{ vsrari('d') }}
 
+{{ vsrarn('b', 'h') }}
+{{ vsrarn('h', 'w') }}
+{{ vsrarn('w', 'd') }}
 
 {{ vsrl('b') }}
 {{ vsrl('h') }}
@@ -118,6 +121,9 @@ Compute 128-bit `a` shifted right by `imm * 8` bits.
 {{ vsrlri('w') }}
 {{ vsrlri('d') }}
 
+{{ vsrlrn('b', 'h') }}
+{{ vsrlrn('h', 'w') }}
+{{ vsrlrn('w', 'd') }}
 
 {{ vrotr('b') }}
 {{ vrotr('h') }}

main.py

@@ -1047,4 +1047,24 @@ def vsrani(name, name2):
             intrinsic=f"__m128i __lsx_vsrani_{name}_{name2} (__m128i a, __m128i b, imm0_{width2-1} imm)",
             instr=f"vsrani.{name}.{name2} vr, vr, imm",
             desc=f"Arithemtic right shift the signed {width2}-bit elements in `a` and `b` by `imm`, truncate to {width}-bit and store the result to `dst`.",
+        )
+
+    @env.macro
+    def vsrlrn(name, name2):
+        width = widths[name[0]]
+        width2 = widths[name2[0]]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsrlrn_{name}_{name2} (__m128i a, __m128i b)",
+            instr=f"vsrlrn.{name}.{name2} vr, vr, vr",
+            desc=f"Logical right shift (with rounding) the unsigned {width2}-bit elements in `a` by elements in `b`, truncate to {width}-bit and store the result to `dst`.",
+        )
+
+    @env.macro
+    def vsrarn(name, name2):
+        width = widths[name[0]]
+        width2 = widths[name2[0]]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsrarn_{name}_{name2} (__m128i a, __m128i b)",
+            instr=f"vsrarn.{name}.{name2} vr, vr, vr",
+            desc=f"Arithmetic right shift (with rounding) the signed {width2}-bit elements in `a` by elements in `b`, truncate to {width}-bit and store the result to `dst`.",
         )