Add vsllwil

README.md

@@ -124,10 +124,6 @@ TODO List:
 
 ### vftintrneh.l.s
 
-### vsllwil.h.b/w.h/d.w
-
-### vsllwil.hu.bu/wu.hu/du.wu
-
 ### vsat.b/h/w/d/bu/hu/wu/du
 
 ### vsrlni.b.h/h.w/w.d/d.q

code/gen_impl.py

@@ -113,6 +113,14 @@
             file=f,
         )
         print(f"}}", file=f)
+    if "width" != "q":
+        with open(f"vsllwil_{double_width}_{width}.h", "w") as f:
+            print(f"for (int i = 0;i < {128 // double_w};i++) {{", file=f)
+            print(
+                f"  dst.{double_m}[i] = ({sign}{double_w})({sign}{w})a.{m}[i] << imm;",
+                file=f,
+            )
+            print(f"}}", file=f)
 
     if width == "d" or width == "du":
         with open(f"vextl_{double_width}_{width}.h", "w") as f:

code/gen_tb.py

@@ -5,6 +5,7 @@
 widths_fp = ["s", "d"]
 widths_all = ["b", "bu", "h", "hu", "w", "wu", "d", "du"]
 widths_vexth = ["h_b", "hu_bu", "w_h", "wu_hu", "d_w", "du_wu", "q_d", "qu_du"]
+widths_vsllwil = ["h_b", "hu_bu", "w_h", "wu_hu", "d_w", "du_wu"]
 widths_vaddw = [
     "h_b",
     "h_bu",
@@ -96,6 +97,7 @@
     "vseqi": (widths_signed, "v128 a, int imm", [-16, 0, 15]),
     "vshuf4i": (["b", "h", "w"], "v128 a, int imm", [0, 13, 100, 128, 255]),
     "vsigncov": (widths_signed, "v128 a, v128 b"),
+    "vsllwil": (widths_vsllwil, "v128 a, int imm", [0, 7]),
     "vssub": (widths_all, "v128 a, v128 b"),
     "vsub": (widths_signed, "v128 a, v128 b"),
     "vsubi": (widths_unsigned, "v128 a, int imm", [0, 31]),

code/vsetallnez_b.h

@@ -1,5 +1,5 @@
 dst = 1;
-for (int i = 0;i < 16;i++) {
+for (int i = 0; i < 16; i++) {
   if (a.byte[i] == 0) {
     dst = 0;
   }

code/vsetallnez_d.h

@@ -1,5 +1,5 @@
 dst = 1;
-for (int i = 0;i < 2;i++) {
+for (int i = 0; i < 2; i++) {
   if (a.dword[i] == 0) {
     dst = 0;
   }

code/vsetallnez_h.h

@@ -1,5 +1,5 @@
 dst = 1;
-for (int i = 0;i < 8;i++) {
+for (int i = 0; i < 8; i++) {
   if (a.half[i] == 0) {
     dst = 0;
   }

code/vsetallnez_w.h

@@ -1,5 +1,5 @@
 dst = 1;
-for (int i = 0;i < 4;i++) {
+for (int i = 0; i < 4; i++) {
   if (a.word[i] == 0) {
     dst = 0;
   }

code/vsetanyeqz_b.h

@@ -1,5 +1,5 @@
 dst = 0;
-for (int i = 0;i < 16;i++) {
+for (int i = 0; i < 16; i++) {
   if (a.byte[i] == 0) {
     dst = 1;
   }

code/vsetanyeqz_d.h

@@ -1,5 +1,5 @@
 dst = 0;
-for (int i = 0;i < 2;i++) {
+for (int i = 0; i < 2; i++) {
   if (a.dword[i] == 0) {
     dst = 1;
   }

code/vsetanyeqz_h.h

@@ -1,5 +1,5 @@
 dst = 0;
-for (int i = 0;i < 8;i++) {
+for (int i = 0; i < 8; i++) {
   if (a.half[i] == 0) {
     dst = 1;
   }

code/vsetanyeqz_w.h

@@ -1,5 +1,5 @@
 dst = 0;
-for (int i = 0;i < 4;i++) {
+for (int i = 0; i < 4; i++) {
   if (a.word[i] == 0) {
     dst = 1;
   }

code/vsllwil_d_w.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsllwil_d_w(v128 a, int imm) {
+  v128 dst;
+#include "vsllwil_d_w.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsllwil_d_w, 0);
+  FUZZ1(vsllwil_d_w, 7);
+}

code/vsllwil_d_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (s64)(s32)a.word[i] << imm;
+}

code/vsllwil_du_wu.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsllwil_du_wu(v128 a, int imm) {
+  v128 dst;
+#include "vsllwil_du_wu.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsllwil_du_wu, 0);
+  FUZZ1(vsllwil_du_wu, 7);
+}

code/vsllwil_du_wu.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (u64)(u32)a.word[i] << imm;
+}

code/vsllwil_h_b.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsllwil_h_b(v128 a, int imm) {
+  v128 dst;
+#include "vsllwil_h_b.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsllwil_h_b, 0);
+  FUZZ1(vsllwil_h_b, 7);
+}

code/vsllwil_h_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (s16)(s8)a.byte[i] << imm;
+}

code/vsllwil_hu_bu.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsllwil_hu_bu(v128 a, int imm) {
+  v128 dst;
+#include "vsllwil_hu_bu.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsllwil_hu_bu, 0);
+  FUZZ1(vsllwil_hu_bu, 7);
+}

code/vsllwil_hu_bu.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (u16)(u8)a.byte[i] << imm;
+}

code/vsllwil_q_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 1; i++) {
+  dst.qword[i] = (s128)(s64)a.dword[i] << imm;
+}

code/vsllwil_qu_du.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 1; i++) {
+  dst.qword[i] = (u128)(u64)a.dword[i] << imm;
+}

code/vsllwil_w_h.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsllwil_w_h(v128 a, int imm) {
+  v128 dst;
+#include "vsllwil_w_h.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsllwil_w_h, 0);
+  FUZZ1(vsllwil_w_h, 7);
+}

code/vsllwil_w_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (s32)(s16)a.half[i] << imm;
+}

code/vsllwil_wu_hu.cpp

@@ -0,0 +1,12 @@
+#include "common.h"
+
+v128 vsllwil_wu_hu(v128 a, int imm) {
+  v128 dst;
+#include "vsllwil_wu_hu.h"
+  return dst;
+}
+
+void test() {
+  FUZZ1(vsllwil_wu_hu, 0);
+  FUZZ1(vsllwil_wu_hu, 7);
+}

code/vsllwil_wu_hu.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (u32)(u16)a.half[i] << imm;
+}

docs/lsx/shift.md

@@ -52,6 +52,13 @@ Compute 128-bit `a` shifted right by `imm * 8` bits.
 {{ vslli('w') }}
 {{ vslli('d') }}
 
+{{ vsllwil('h', 'b') }}
+{{ vsllwil('hu', 'bu') }}
+{{ vsllwil('w', 'h') }}
+{{ vsllwil('wu', 'hu') }}
+{{ vsllwil('d', 'w') }}
+{{ vsllwil('du', 'wu') }}
+
 {{ vsrl('b') }}
 {{ vsrl('h') }}
 {{ vsrl('w') }}

main.py

@@ -996,4 +996,15 @@ def bnz(name):
             intrinsic=f"int __lsx_bnz_{name} (__m128i a)",
             instr=f"vsetallnez.{name} vr, vr; bcnez",
             desc=f"Expected to be used in branches: branch if all {width}-bit elements in `a` are non-zero.",
+        )
+
+    @env.macro
+    def vsllwil(name, name2):
+        width = widths[name[0]]
+        width2 = widths[name2[0]]
+        signedness = signednesses[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsllwil_{name}_{name2} (__m128i a, imm0_{width2-1} imm)",
+            instr=f"vsllwil.{name}.{name2} vr, vr, imm",
+            desc=f"Extend and shift {signedness} {width2}-bit elements in `a` by `imm` to {signedness} {width}-bit result.",
         )