Fix unsigned typo, vminmaxi

jiegec · Dec 13, 2023 · 4f3c89f · 4f3c89f
1 parent 7d34c32
commit 4f3c89f
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Showing 3 changed files with 9 additions and 7 deletions.
diff --git a/check_lsx.py b/check_lsx.py
@@ -42,4 +42,6 @@ def parse_fn(line, skip_last):
     print("Undocumented:", " ".join(entry))
     for e in documented_intrinsics:
         if e[1] == entry[1]:
-            print("Matching:", " ".join(e))
+            print("Matching:", " ".join(e))
+            print(repr(e))
+            print(repr(entry))
diff --git a/gcc_lsxintrin.h b/gcc_lsxintrin.h
@@ -444,11 +444,11 @@ __m128i __lsx_vpickod_d (__m128i, __m128i);
 __m128i __lsx_vpickod_h (__m128i, __m128i);
 __m128i __lsx_vpickod_w (__m128i, __m128i);
 int __lsx_vpickve2gr_b (__m128i, imm0_15);
-unsinged int __lsx_vpickve2gr_bu (__m128i, imm0_15);
+unsigned int __lsx_vpickve2gr_bu (__m128i, imm0_15);
 long int __lsx_vpickve2gr_d (__m128i, imm0_1);
 unsigned long int __lsx_vpickve2gr_du (__m128i, imm0_1);
 int __lsx_vpickve2gr_h (__m128i, imm0_7);
-unsinged int __lsx_vpickve2gr_hu (__m128i, imm0_7);
+unsigned int __lsx_vpickve2gr_hu (__m128i, imm0_7);
 int __lsx_vpickve2gr_w (__m128i, imm0_3);
 unsigned int __lsx_vpickve2gr_wu (__m128i, imm0_3);
 __m128i __lsx_vreplgr2vr_b (int);

diff --git a/main.py b/main.py
@@ -523,7 +523,7 @@ def vminmaxi(min_max, name):
         else:
             imm_range = "n16_15"
         return instruction(
-            intrinsic=f"__m128i __lsx_v{min_max}i_{name} (__m128i a, imm_{imm_range} imm)",
+            intrinsic=f"__m128i __lsx_v{min_max}i_{name} (__m128i a, imm{imm_range} imm)",
             instr=f"v{min_max}i.{name} vr, vr, imm",
             desc=f"Compute elementwise {min_max}imum for {signedness} {width}-bit elements in `a` and `imm`.",
         )
@@ -754,9 +754,9 @@ def vssub(name):
         width = widths[name]
         signedness = signednesses[name]
         return instruction(
-            intrinsic=f"__m128i __lsx_vsadd_{name} (__m128i a, __m128i b)",
-            instr=f"vsadd.{name} vr, vr, vr",
-            desc=f"Saturing add the {signedness} {width}-bit elements in `a` and `b`, store the result to `dst`.",
+            intrinsic=f"__m128i __lsx_vssub_{name} (__m128i a, __m128i b)",
+            instr=f"vssub.{name} vr, vr, vr",
+            desc=f"Saturing subtract the {signedness} {width}-bit elements in `a` and `b`, store the result to `dst`.",
         )
 
     @env.macro