Add vexth

README.md

@@ -118,12 +118,8 @@ Vector Multiplication High
 
 ### vmaddwod.h.bu/w.hu/d.wu/q.du
 
-### vdiv.b/h/w/d
-
 ### vmod.b/h/w/d
 
-### vdiv.bu/hu/wu/du
-
 ### vmod.bu/hu/wu/du
 
 ### vsll.b/h/w/d
@@ -332,8 +328,6 @@ Vector Multiplication High
 
 ### vftintrneh.l.s
 
-### vexth.h.b/w.h/d.w/q.d/hu.bu/wu.hu/du.wu/qu.du
-
 ### vreplgr2vr.b/h/w/d
 
 ### vrotri.b/h/w/d

code/gen_impl.py

@@ -24,6 +24,17 @@
     "du": "q",
 }
 
+double_widths_same_signedness = {
+    "b": "h",
+    "bu": "hu",
+    "h": "w",
+    "hu": "wu",
+    "w": "d",
+    "wu": "du",
+    "d": "q",
+    "du": "qu",
+}
+
 members = {
     "b": "byte",
     "bu": "byte",
@@ -65,6 +76,16 @@
             file=f,
         )
         print(f"}}", file=f)
+    double_width = double_widths_same_signedness[width]
+    double_w = widths[double_width]
+    double_m = members[double_width]
+    with open(f"vexth_{double_width}_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // double_w};i++) {{", file=f)
+        print(
+            f"  dst.{double_m}[i] = ({sign}{double_w})({sign}{w})a.{m}[{128 // double_w} + i];",
+            file=f,
+        )
+        print(f"}}", file=f)
 
 for width in ["b", "bu", "h", "hu", "w", "wu", "d", "du"]:
     double_width = double_widths[width]

code/gen_tb.py

@@ -2,6 +2,16 @@
 
 widths_signed = ["b", "h", "w", "d"]
 widths_all = ["b", "bu", "h", "hu", "w", "wu", "d", "du"]
+widths_vexth = [
+    "h_b",
+    "hu_bu",
+    "w_h",
+    "wu_hu",
+    "d_w",
+    "du_wu",
+    "q_d",
+    "qu_du"
+]
 widths_vaddw = [
     "h_b",
     "h_bu",
@@ -32,6 +42,7 @@
     "vclo": (widths_signed, "v128 a"),
     "vclz": (widths_signed, "v128 a"),
     "vdiv": (widths_all, "v128 a, v128 b"),
+    "vexth": (widths_vexth, "v128 a"),
 }
 
 for name in tb:

code/vexth_d_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vexth_d_w(v128 a) {
+  v128 dst;
+#include "vexth_d_w.h"
+  return dst;
+}
+
+void test() { FUZZ1(vexth_d_w); }

code/vexth_d_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (s64)(s32)a.word[2 + i];
+}

code/vexth_du_wu.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vexth_du_wu(v128 a) {
+  v128 dst;
+#include "vexth_du_wu.h"
+  return dst;
+}
+
+void test() { FUZZ1(vexth_du_wu); }

code/vexth_du_wu.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (u64)(u32)a.word[2 + i];
+}

code/vexth_h_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vexth_h_b(v128 a) {
+  v128 dst;
+#include "vexth_h_b.h"
+  return dst;
+}
+
+void test() { FUZZ1(vexth_h_b); }

code/vexth_h_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (s16)(s8)a.byte[8 + i];
+}

code/vexth_hu_bu.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vexth_hu_bu(v128 a) {
+  v128 dst;
+#include "vexth_hu_bu.h"
+  return dst;
+}
+
+void test() { FUZZ1(vexth_hu_bu); }

code/vexth_hu_bu.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (u16)(u8)a.byte[8 + i];
+}

code/vexth_q_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vexth_q_d(v128 a) {
+  v128 dst;
+#include "vexth_q_d.h"
+  return dst;
+}
+
+void test() { FUZZ1(vexth_q_d); }

code/vexth_q_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 1; i++) {
+  dst.qword[i] = (s128)(s64)a.dword[1 + i];
+}

code/vexth_qu_du.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vexth_qu_du(v128 a) {
+  v128 dst;
+#include "vexth_qu_du.h"
+  return dst;
+}
+
+void test() { FUZZ1(vexth_qu_du); }

code/vexth_qu_du.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 1; i++) {
+  dst.qword[i] = (u128)(u64)a.dword[1 + i];
+}

code/vexth_w_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vexth_w_h(v128 a) {
+  v128 dst;
+#include "vexth_w_h.h"
+  return dst;
+}
+
+void test() { FUZZ1(vexth_w_h); }

code/vexth_w_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (s32)(s16)a.half[4 + i];
+}

code/vexth_wu_hu.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vexth_wu_hu(v128 a) {
+  v128 dst;
+#include "vexth_wu_hu.h"
+  return dst;
+}
+
+void test() { FUZZ1(vexth_wu_hu); }

code/vexth_wu_hu.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (u32)(u16)a.half[4 + i];
+}

docs/lsx/bitwise.md

@@ -80,4 +80,13 @@ Compute bitwise selection: for each bit position, if the bit in `a` equals to on
 {{ vclz('b') }}
 {{ vclz('h') }}
 {{ vclz('w') }}
-{{ vclz('d') }}
+{{ vclz('d') }}
+
+{{ vexth('h', 'b') }}
+{{ vexth('hu', 'bu') }}
+{{ vexth('w', 'h') }}
+{{ vexth('wu', 'hu') }}
+{{ vexth('d', 'w') }}
+{{ vexth('du', 'wu') }}
+{{ vexth('q', 'd') }}
+{{ vexth('qu', 'du') }}

main.py

@@ -24,6 +24,7 @@ def define_env(env):
         "d": "signed",
         "du": "unsigned",
         "q": "signed",
+        "qu": "unsigned",
     }
 
     def include(file):
@@ -234,10 +235,22 @@ def vclz(name):
     @env.macro
     def vdiv(name):
         width = widths[name]
+        signedness = signednesses[name]
         return instruction(
             intrinsic=f"__m128i __lsx_div_{name} (__m128i a, __m128i b)",
             instr=f"vdiv.{name} vr, vr, vr",
-            desc=f"Divide {width}-bit elements in `a` by elements in `b`.",
+            desc=f"Divide {signedness} {width}-bit elements in `a` by elements in `b`.",
+        )
+
+    @env.macro
+    def vexth(name, name2):
+        width = widths[name[0]]
+        width2 = widths[name2[0]]
+        signedness = signednesses[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vexth_{name}_{name2} (__m128i a)",
+            instr=f"vexth.{name}.{name2} vr, vr",
+            desc=f"Extend {signedness} {width2}-bit elements in the higher half of `a` to {width}-bit.",
         )
 
     @env.macro