Fix typo, move ext intrinsics to misc

jiegec · Dec 16, 2023 · 72de998 · 72de998
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Showing 6 changed files with 39 additions and 38 deletions.
diff --git a/docs/lasx/bitwise_operations.md b/docs/lasx/bitwise_operations.md
@@ -44,23 +44,6 @@
 {{ xvclz('w') }}
 {{ xvclz('d') }}
 
-{{ xvexth('h', 'b') }}
-{{ xvexth('hu', 'bu') }}
-{{ xvexth('w', 'h') }}
-{{ xvexth('wu', 'hu') }}
-{{ xvexth('d', 'w') }}
-{{ xvexth('du', 'wu') }}
-{{ xvexth('q', 'd') }}
-{{ xvexth('qu', 'du') }}
-
-{{ xvextl('q', 'd') }}
-{{ xvextl('qu', 'du') }}
-
-{{ xvextrins('b') }}
-{{ xvextrins('h') }}
-{{ xvextrins('w') }}
-{{ xvextrins('d') }}
-
 {{ xvpcnt('b') }}
 {{ xvpcnt('h') }}
 {{ xvpcnt('w') }}

diff --git a/docs/lasx/misc.md b/docs/lasx/misc.md
@@ -1,5 +1,22 @@
 # Misc
 
+{{ xvexth('h', 'b') }}
+{{ xvexth('hu', 'bu') }}
+{{ xvexth('w', 'h') }}
+{{ xvexth('wu', 'hu') }}
+{{ xvexth('d', 'w') }}
+{{ xvexth('du', 'wu') }}
+{{ xvexth('q', 'd') }}
+{{ xvexth('qu', 'du') }}
+
+{{ xvextl('q', 'd') }}
+{{ xvextl('qu', 'du') }}
+
+{{ xvextrins('b') }}
+{{ xvextrins('h') }}
+{{ xvextrins('w') }}
+{{ xvextrins('d') }}
+
 {{ vext2xv('h', 'b') }}
 {{ vext2xv('hu', 'bu') }}
 {{ vext2xv('w', 'b') }}

diff --git a/docs/lsx/bitwise_operations.md b/docs/lsx/bitwise_operations.md
@@ -44,23 +44,6 @@
 {{ vclz('w') }}
 {{ vclz('d') }}
 
-{{ vexth('h', 'b') }}
-{{ vexth('hu', 'bu') }}
-{{ vexth('w', 'h') }}
-{{ vexth('wu', 'hu') }}
-{{ vexth('d', 'w') }}
-{{ vexth('du', 'wu') }}
-{{ vexth('q', 'd') }}
-{{ vexth('qu', 'du') }}
-
-{{ vextl('q', 'd') }}
-{{ vextl('qu', 'du') }}
-
-{{ vextrins('b') }}
-{{ vextrins('h') }}
-{{ vextrins('w') }}
-{{ vextrins('d') }}
-
 {{ vpcnt('b') }}
 {{ vpcnt('h') }}
 {{ vpcnt('w') }}

diff --git a/docs/lsx/misc.md b/docs/lsx/misc.md
@@ -1,5 +1,23 @@
 # Misc
 
+{{ vexth('h', 'b') }}
+{{ vexth('hu', 'bu') }}
+{{ vexth('w', 'h') }}
+{{ vexth('wu', 'hu') }}
+{{ vexth('d', 'w') }}
+{{ vexth('du', 'wu') }}
+{{ vexth('q', 'd') }}
+{{ vexth('qu', 'du') }}
+
+{{ vextl('q', 'd') }}
+{{ vextl('qu', 'du') }}
+
+{{ vextrins('b') }}
+{{ vextrins('h') }}
+{{ vextrins('w') }}
+{{ vextrins('d') }}
+
+
 {{ vilvh('b') }}
 {{ vilvh('h') }}
 {{ vilvh('w') }}

diff --git a/docs/migrating_sse.md b/docs/migrating_sse.md
@@ -12,9 +12,9 @@ Here is a table of a mapping from SSE intrinsics to their LSX counterpart (WIP):
 
 | SSE                     | LSX                                   |
 |-------------------------|---------------------------------------|
-| _mm_abs_epi16           |                                       |
-| _mm_abs_epi32           |                                       |
-| _mm_abs_epi8            |                                       |
+| _mm_abs_epi16           | __lsx_vsigncov_h                      |
+| _mm_abs_epi32           | __lsx_vsigncov_w                      |
+| _mm_abs_epi8            | __lsx_vsigncov_b                      |
 | _mm_add_epi16           | __lsx_vadd_h                          |
 | _mm_add_epi32           | __lsx_vadd_w                          |
 | _mm_add_epi64           | __lsx_vadd_d                          |

diff --git a/main.py b/main.py
@@ -1089,7 +1089,7 @@ def vsigncov(name):
         return instruction(
             intrinsic=f"__m128i __lsx_vsigncov_{name} (__m128i a, __m128i b)",
             instr=f"vsigncov.{name} vr, vr, vr",
-            desc=f"If the {width}-bit element in `a` equals to zero, set the result to zero. If the signed {width}-bit element in `a` is posiive, copy element in `b` to result. Otherwise, copy negated element in `b` to result.",
+            desc=f"If the {width}-bit element in `a` equals to zero, set the result to zero. If the signed {width}-bit element in `a` is positive, copy element in `b` to result. Otherwise, copy negated element in `b` to result. If `a` and `b` are the same vectors, it is equivalent to computing absolute value.",
         )
 
     @my_macro(env)