Add vsub

README.md

@@ -22,10 +22,6 @@ Vector Store with Register Offset
 
 Vector Set Equal/Less than or Equal/Less Than
 
-### vsub.b/h/w/d
-
-Vector Subtract
-
 ### vsadd.b/h/w/d
 
 Vector Saturated Add
@@ -124,8 +120,6 @@ Vector Multiplication High
 
 ### vfrstp.b/h
 
-### vsub.q
-
 ### vsignconv.b/h/w/d
 
 ### vfsub.s/d

code/gen_impl.py

@@ -186,6 +186,14 @@
 for width in ["b", "h", "w", "d"]:
     w = widths[width]
     m = members[width]
+    for name, op in [("add", "+"), ("sub", "-")]:
+        with open(f"v{name}_{width}.h", "w") as f:
+            print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+            print(
+                f"  dst.{m}[i] = a.{m}[i] {op} b.{m}[i];",
+                file=f,
+            )
+            print(f"}}", file=f)
     with open(f"vbitclr_{width}.h", "w") as f:
         print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
         print(

code/gen_tb.py

@@ -31,6 +31,7 @@
 
 tb = {
     # widths, args, extra args for imm
+    "vadd": (widths_signed, "v128 a, v128 b"),
     "vavg": (widths_all, "v128 a, v128 b"),
     "vavgr": (widths_all, "v128 a, v128 b"),
     "vaddwev": (widths_vaddw, "v128 a, v128 b"),
@@ -66,6 +67,7 @@
     "vmini": (widths_all, "v128 a, int imm", [0, 3, 15]),
     "vmulwev": (widths_vaddw, "v128 a, v128 b"),
     "vmulwod": (widths_vaddw, "v128 a, v128 b"),
+    "vsub": (widths_signed, "v128 a, v128 b"),
     "vsubwev": (widths_vsubw, "v128 a, v128 b"),
     "vsubwod": (widths_vsubw, "v128 a, v128 b"),
 }

code/vadd_b.h

@@ -1,3 +1,3 @@
 for (int i = 0; i < 16; i++) {
   dst.byte[i] = a.byte[i] + b.byte[i];
-}
+}

code/vsub_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsub_b(v128 a, v128 b) {
+  v128 dst;
+#include "vsub_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsub_b); }

code/vsub_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = a.byte[i] - b.byte[i];
+}

code/vsub_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsub_d(v128 a, v128 b) {
+  v128 dst;
+#include "vsub_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsub_d); }

code/vsub_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = a.dword[i] - b.dword[i];
+}

code/vsub_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsub_h(v128 a, v128 b) {
+  v128 dst;
+#include "vsub_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsub_h); }

code/vsub_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = a.half[i] - b.half[i];
+}

code/vsub_q.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsub_q(v128 a, v128 b) {
+  v128 dst;
+#include "vsub_q.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsub_q); }

code/vsub_q.h

@@ -0,0 +1 @@
+dst.qword[0] = a.qword[0] - b.qword[0];

code/vsub_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsub_w(v128 a, v128 b) {
+  v128 dst;
+#include "vsub_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsub_w); }

code/vsub_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = a.word[i] - b.word[i];
+}

docs/lsx/integer_computation.md

@@ -145,6 +145,13 @@
 {{ vmulwev('q', 'du') }}
 {{ vmulwev('q', 'du', 'd') }}
 
+{{ vsub('b') }}
+{{ vsub('h') }}
+{{ vsub('w') }}
+{{ vsub('d') }}
+{{ vsub('q') }}
+
+
 {{ vsubwev('h', 'b') }}
 {{ vsubwev('h', 'bu') }}
 {{ vsubwev('w', 'h') }}

main.py

@@ -447,3 +447,11 @@ def vldrepl(name):
             desc=f"Read {width}-bit data from memory address `addr + (offset << {shift})`, replicate the data to all vector lanes and save into `dst`.",
         )
 
+    @env.macro
+    def vsub(name):
+        width = widths[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsub_{name} (__m128i a, __m128i b)",
+            instr=f"vsub.{name} vr, vr, vr",
+            desc=f"Subtract {width}-bit elements in `a` and `b`, save the result in `dst`.",
+        )