Add vmuh

README.md

@@ -6,10 +6,6 @@ Arranged from QEMU implementation and [GCC Intrinsics](https://gcc.gnu.org/onlin
 
 TODO List:
 
-### vmuh.b/h/w/d/bu/hu/wu/du
-
-Vector Multiplication High
-
 ### vmod.b/h/w/d
 
 ### vmod.bu/hu/wu/du

code/gen_impl.py

@@ -159,6 +159,13 @@
                 file=f,
             )
             print(f"}}", file=f)
+    with open(f"vmuh_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = ((({sign}{w * 2})({sign}{w})a.{m}[i] * ({sign}{w * 2})({sign}{w})b.{m}[i])) >> {w};",
+            file=f,
+        )
+        print(f"}}", file=f)
 
 for width in ["b", "bu", "h", "hu", "w", "wu", "d", "du"]:
     double_width = double_widths[width]

code/gen_tb.py

@@ -69,6 +69,7 @@
     "vmin": (widths_all, "v128 a, v128 b"),
     "vmini": (widths_all, "v128 a, int imm", [0, 3, 15]),
     "vmsub": (widths_signed, "v128 a, v128 b, v128 c"),
+    "vmuh": (widths_all, "v128 a, v128 b"),
     "vmul": (widths_signed, "v128 a, v128 b"),
     "vmulwev": (widths_vaddw, "v128 a, v128 b"),
     "vmulwod": (widths_vaddw, "v128 a, v128 b"),

code/vmuh_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmuh_b(v128 a, v128 b) {
+  v128 dst;
+#include "vmuh_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vmuh_b); }

code/vmuh_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = (((s16)(s8)a.byte[i] * (s16)(s8)b.byte[i])) >> 8;
+}

code/vmuh_bu.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmuh_bu(v128 a, v128 b) {
+  v128 dst;
+#include "vmuh_bu.h"
+  return dst;
+}
+
+void test() { FUZZ2(vmuh_bu); }

code/vmuh_bu.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = (((u16)(u8)a.byte[i] * (u16)(u8)b.byte[i])) >> 8;
+}

code/vmuh_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmuh_d(v128 a, v128 b) {
+  v128 dst;
+#include "vmuh_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vmuh_d); }

code/vmuh_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (((s128)(s64)a.dword[i] * (s128)(s64)b.dword[i])) >> 64;
+}

code/vmuh_du.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmuh_du(v128 a, v128 b) {
+  v128 dst;
+#include "vmuh_du.h"
+  return dst;
+}
+
+void test() { FUZZ2(vmuh_du); }

code/vmuh_du.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (((u128)(u64)a.dword[i] * (u128)(u64)b.dword[i])) >> 64;
+}

code/vmuh_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmuh_h(v128 a, v128 b) {
+  v128 dst;
+#include "vmuh_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vmuh_h); }

code/vmuh_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (((s32)(s16)a.half[i] * (s32)(s16)b.half[i])) >> 16;
+}

code/vmuh_hu.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmuh_hu(v128 a, v128 b) {
+  v128 dst;
+#include "vmuh_hu.h"
+  return dst;
+}
+
+void test() { FUZZ2(vmuh_hu); }

code/vmuh_hu.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (((u32)(u16)a.half[i] * (u32)(u16)b.half[i])) >> 16;
+}

code/vmuh_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmuh_w(v128 a, v128 b) {
+  v128 dst;
+#include "vmuh_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vmuh_w); }

code/vmuh_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (((s64)(s32)a.word[i] * (s64)(s32)b.word[i])) >> 32;
+}

code/vmuh_wu.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vmuh_wu(v128 a, v128 b) {
+  v128 dst;
+#include "vmuh_wu.h"
+  return dst;
+}
+
+void test() { FUZZ2(vmuh_wu); }

code/vmuh_wu.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (((u64)(u32)a.word[i] * (u64)(u32)b.word[i])) >> 32;
+}

docs/lsx/integer_computation.md

@@ -168,6 +168,15 @@
 {{ vmsub('w') }}
 {{ vmsub('d') }}
 
+{{ vmuh('b') }}
+{{ vmuh('bu') }}
+{{ vmuh('h') }}
+{{ vmuh('hu') }}
+{{ vmuh('w') }}
+{{ vmuh('wu') }}
+{{ vmuh('d') }}
+{{ vmuh('du') }}
+
 {{ vmul('b') }}
 {{ vmul('h') }}
 {{ vmul('w') }}

main.py

@@ -517,6 +517,16 @@ def vmul(name):
             desc=f"Multiply {width}-bit elements in `a` and `b`, save the result in `dst`.",
         )
 
+    @env.macro
+    def vmuh(name):
+        width = widths[name]
+        signedness = signednesses[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vmuh_{name} (__m128i a, __m128i b)",
+            instr=f"vmuh.{name} vr, vr, vr",
+            desc=f"Multiply {signedness} {width}-bit elements in `a` and `b`, save the high {width}-bit result in `dst`.",
+        )
+
     @env.macro
     def vmsub(name):
         width = widths[name]