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chore: support for DMA value reading
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@joamag
joamag committed Feb 25, 2024
1 parent 9844d40 commit f2f7d6b
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Showing 2 changed files with 43 additions and 39 deletions.
30 changes: 16 additions & 14 deletions src/dma.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@ pub struct Dma {
length: u16,
pending: u16,
mode: DmaMode,
cycles_dma: u16,
value_dma: u8,
cycles_dma: u16,
active_dma: bool,
active_hdma: bool,
}
Expand All @@ -29,8 +29,8 @@ impl Dma {
length: 0x0,
pending: 0x0,
mode: DmaMode::General,
cycles_dma: 0x0,
value_dma: 0x0,
cycles_dma: 0x0,
active_dma: false,
active_hdma: false,
}
Expand All @@ -42,8 +42,8 @@ impl Dma {
self.length = 0x0;
self.pending = 0x0;
self.mode = DmaMode::General;
self.cycles_dma = 0x0;
self.value_dma = 0x0;
self.cycles_dma = 0x0;
self.active_dma = false;
self.active_hdma = false;
}
Expand All @@ -52,6 +52,8 @@ impl Dma {

pub fn read(&mut self, addr: u16) -> u8 {
match addr {
// 0xFF46 — DMA: OAM DMA source address & start
DMA_ADDR => self.value_dma,
// 0xFF55 — HDMA5: VRAM DMA length/mode/start (CGB only)
HDMA5_ADDR => {
((self.pending >> 4) as u8).wrapping_sub(1) | ((!self.active_hdma as u8) << 7)
Expand All @@ -67,8 +69,8 @@ impl Dma {
match addr {
// 0xFF46 — DMA: OAM DMA source address & start
DMA_ADDR => {
self.cycles_dma = 640;
self.value_dma = value;
self.cycles_dma = 640;
self.active_dma = true;
}
// 0xFF51 — HDMA1: VRAM DMA source high (CGB only)
Expand Down Expand Up @@ -134,14 +136,6 @@ impl Dma {
self.mode = value;
}

pub fn cycles_dma(&self) -> u16 {
self.cycles_dma
}

pub fn set_cycles_dma(&mut self, value: u16) {
self.cycles_dma = value;
}

pub fn value_dma(&self) -> u8 {
self.value_dma
}
Expand All @@ -150,6 +144,14 @@ impl Dma {
self.value_dma = value;
}

pub fn cycles_dma(&self) -> u16 {
self.cycles_dma
}

pub fn set_cycles_dma(&mut self, value: u16) {
self.cycles_dma = value;
}

pub fn active_dma(&self) -> bool {
self.active_dma
}
Expand Down Expand Up @@ -197,8 +199,8 @@ mod tests {
dma.length = 0x9abc;
dma.pending = 0x9abc;
dma.mode = DmaMode::HBlank;
dma.cycles_dma = 0x0012;
dma.value_dma = 0xff;
dma.cycles_dma = 0x0012;
dma.active_dma = true;
dma.active_hdma = true;

Expand All @@ -209,8 +211,8 @@ mod tests {
assert_eq!(dma.length, 0x0);
assert_eq!(dma.pending, 0x0);
assert_eq!(dma.mode, DmaMode::General);
assert_eq!(dma.cycles_dma, 0x0);
assert_eq!(dma.value_dma, 0x0);
assert_eq!(dma.cycles_dma, 0x0);
assert!(!dma.active_dma);
assert!(!dma.active_hdma);
}
Expand Down
52 changes: 27 additions & 25 deletions src/mmu.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -397,7 +397,13 @@ impl Mmu {
}
},
0x10 | 0x20 | 0x30 => self.apu.read(addr),
0x40 | 0x60 | 0x70 => self.ppu.read(addr),
0x40 | 0x60 | 0x70 => match addr & 0x00ff {
// 0xFF46 — DMA: OAM DMA source address & start
0x0046 => self.dma.read(addr),

// VRAM related read
_ => self.ppu.read(addr),
},
0x50 => match addr & 0x00ff {
0x51..=0x55 => self.dma.read(addr),
_ => {
Expand Down Expand Up @@ -497,31 +503,27 @@ impl Mmu {
0xff => self.ie = value,

// Other registers
_ => {
match addr & 0x00f0 {
0x00 => match addr & 0x00ff {
0x00 => self.pad.write(addr, value),
0x04..=0x07 => self.timer.write(addr, value),
_ => debugln!("Writing to unknown IO control 0x{:04x}", addr),
},
0x10 | 0x20 | 0x30 => self.apu.write(addr, value),
0x40 | 0x60 | 0x70 => {
match addr & 0x00ff {
// 0xFF46 — DMA: OAM DMA source address & start
0x0046 => self.dma.write(addr, value),

// VRAM related write
_ => self.ppu.write(addr, value),
}
}
#[allow(clippy::single_match)]
0x50 => match addr & 0x00ff {
0x51..=0x55 => self.dma.write(addr, value),
_ => debugln!("Writing to unknown IO control 0x{:04x}", addr),
},
_ => match addr & 0x00f0 {
0x00 => match addr & 0x00ff {
0x00 => self.pad.write(addr, value),
0x04..=0x07 => self.timer.write(addr, value),
_ => debugln!("Writing to unknown IO control 0x{:04x}", addr),
}
}
},
0x10 | 0x20 | 0x30 => self.apu.write(addr, value),
0x40 | 0x60 | 0x70 => match addr & 0x00ff {
// 0xFF46 — DMA: OAM DMA source address & start
0x0046 => self.dma.write(addr, value),

// VRAM related write
_ => self.ppu.write(addr, value),
},
#[allow(clippy::single_match)]
0x50 => match addr & 0x00ff {
0x51..=0x55 => self.dma.write(addr, value),
_ => debugln!("Writing to unknown IO control 0x{:04x}", addr),
},
_ => debugln!("Writing to unknown IO control 0x{:04x}", addr),
},
},
addr => panic!("Writing to unknown location 0x{:04x}", addr),
},
Expand Down

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