Squashed commit of the following:

commit 78d1bce
Author: Leonard Pfeiffer <[email protected]>
Date:   Sun Oct 29 20:21:22 2023 +0100

    Update Quartus project files (#17)

commit 8276bc1
Author: Leonard Pfeiffer <[email protected]>
Date:   Sun Oct 29 17:37:02 2023 +0100

    Update pin assignments for lowactive toplevel ports (#15)

commit 73d39a5
Author: Leonard Pfeiffer <[email protected]>
Date:   Sun Oct 29 17:20:01 2023 +0100

    Add utils (#16)

    Add
    - Pwm generator
    - Clock enable generator
    - Clock splitter

commit 415aa1a
Author: Leonard Pfeiffer <[email protected]>
Date:   Sat Oct 28 22:56:48 2023 +0200

    Create and set up Quartus project (#13)

    * Create quartus project

    - Add toplevel entity
    - Add toplevel package
    - Add quartus project
    - Add pin assignments
    - Remove quartus dbs and outputs from gitignore

commit 09bd586
Author: Leonard Pfeiffer <[email protected]>
Date:   Fri Oct 27 16:32:35 2023 +0200

    Repair gitignore remove comment in include statement #12

commit 05f9d53
Merge: 97cf2e1 dfa23f3
Author: Leonard Pfeiffer <[email protected]>
Date:   Fri Oct 27 12:20:47 2023 +0200

    Repair .gitignore remove indentations use empty lines instead #11

commit dfa23f3
Author: Leonard Pfeiffer <[email protected]>
Date:   Fri Oct 27 12:16:37 2023 +0200

    Repair .gitignore remove indentations use empty lines instead

.gitignore

@@ -1,33 +1,45 @@
 # General
-  *
-  !*/
-  !*.txt
+*
+!*/
+!*.txt
+
 # VHDL
-  !*.sv         # Note: .sv for SystemVerilog 2006 Standard instead of .v for Verliog 2001 standard
-  !*.vhdl
-  !*.vhd
+# Note: Using .sv for SystemVerilog 2006 Standard instead of .v for Verliog 2001 standard
+!*.sv
+!*.vhdl
+!*.vhd
+
 # Quartus
-  !*.qpf
-  !*.qsf
-  !*.sdc
-  !*.srf
+!*.qpf
+!*.qsf
+!*.sdc
+!*.srf
+
 # Platform Designer (Qsys)
-  !*.qsys
-  !*.qip
-  !*.bsf
+!*.qsys
+!*.qip
+!*.bsf
+
 # Modelsim
-  !*.mpf
-  !*.vqm
-  !*.qrf
-  !*.do
-  !*.tcl
+!*.mpf
+!*.vqm
+!*.qrf
+!*.do
+!*.tcl
+
 # Doc
-  !*.tex
-  !*.md
+!*.tex
+!*.md
+
 # Folders
-  *.vscode/
+*.vscode/
+quartus/db
+quartus/incremental_db
+quartus/output_files
+quartus/simulation
+
 # Software (alpha)
-  *.asm
-  *.c
-  *.cc
-  *.cpp
+*.asm
+*.c
+*.cc
+*.cpp

quartus/MARVIN.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2023  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+# Date created = 16:43:21  Oktober 27, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "22.1"
+DATE = "16:43:21  Oktober 27, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "marvin"