Verilog Examples

Module

module <name>(
    <ports/generics>
);
    <constant-parameters>
    <registers/wires>
    <instances>
    <processes>
    <assignents>
endmodule

Ports

input <name1>,                // Input
input [x:y] <name2>, <name3>, // Multiple array "x downto y" inputs
inout <name4>,                // Simultaneus in- and output
output <name4>                // Output

Registers / Wires

reg <type> <name1>, <name2>; // Registers (Save Data at end of clock cycle)
wire <type> [x:y] <name3>;   // Wire "from x downto y" (Transmits data almost instantly)

Parameters

parameter <type> <name>;           // Generic (in port definition)
parameter <type> <name> = <value>; // Constant

Instantionation

<module> #(
    <parameter-ass1>,
    <parameter-ass2>
) <instance> (
    <port-ass1>,
    <port-ass2>
);

Assignments

.<port>(<connection/value>)
.<parameter(<connection/value>)

Values

0 // Logical zero
1 // Logical one
x // Unknown/undefined
z // What the actual f*ck

Types and actually useful values

Values and their types

-7 46 123      // Integer
1.3 0.2 3e-5   // Real
"Hello kitty!" // String

Radix

d46 D23 // Decimal
hFA HAE // Hexadecimal
o17 O77 // Octal
b10 b01 // Binary

Length

32'd46      // 32 bit filled with decimal 46
8'b10101010 // "10101010" in binary as 8 bit
18'o777777  // 18 bits of ones from octal

Types why is this a subcategory

// Can be interpreted by totally not stupid compiler that will produce untraceable errors
real    // Obvious
string  // Obvious
time    // For simulations
event   // I don't know
integer // Why not in first place?

Processes

Always @

always @ (<condition>) <actions>

Conditions

posedge clk // Rising edge of clock
negedge clk // Falling edge o clock
posedge rst // Rising edge of reset

Assignments

Assign all indices

assign x = '1'; // Assign all indexes to logical one