Initial commit

.github/workflows/scala.yml

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+name: Scala CI
+
+on:
+  push:
+    branches: [ master ]
+  pull_request:
+    branches: [ master ]
+
+permissions:
+  contents: read
+
+jobs:
+  build:
+
+    runs-on: ubuntu-latest
+
+    steps:
+    - uses: actions/checkout@v3
+    - name: Set up JDK 11
+      uses: actions/setup-java@v3
+      with:
+        java-version: '11'
+        distribution: 'temurin'
+    - name: Run tests
+      run: sbt test
+    - name: Generate verilog
+      run: sbt run

Makefile

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+# Generate Verilog code
+doit:
+	sbt run
+
+# Run the test
+test:
+	sbt test
+
+clean:
+	git clean -fd
+

README.md

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+# chisel-empty
+
+An almost empty chisel project as a starting point for hardware design.
+
+See the `Makefile` for the hardware and test targets.

build.sbt

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+scalaVersion := "2.12.13"
+
+scalacOptions ++= Seq(
+  "-feature",
+  "-language:reflectiveCalls",
+)
+
+// Chisel 3.5
+addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.6" cross CrossVersion.full)
+libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.6"
+libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.6"

quartus/add.qpf

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+PROJECT_REVISION = "add"

quartus/add.qsf

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+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE115F29C7
+
+set_global_assignment -name TOP_LEVEL_ENTITY Add
+set_global_assignment -name VERILOG_FILE ../generated/Add.v
+set_global_assignment -name VERILOG_MACRO "SYNTHESIS=<None>"
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+
+
+set_location_assignment PIN_Y2 -to clock
+
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

src/main/scala/empty/Add.scala

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+/*
+ * Dummy file to start a Chisel project.
+ *
+ * Author: Martin Schoeberl ([email protected])
+ * 
+ */
+
+package empty
+
+import chisel3._
+import chisel3.util._
+
+class Add extends Module {
+  val io = IO(new Bundle {
+    val a = Input(UInt(8.W))
+    val b = Input(UInt(8.W))
+    val c = Output(UInt(8.W))
+  })
+
+  val reg = RegInit(0.U(8.W))
+  reg := io.a + io.b
+
+  io.c := reg
+}
+
+object AddMain extends App {
+  println("Generating the adder hardware")
+  emitVerilog(new Add(), Array("--target-dir", "generated"))
+}

src/test/scala/empty/AddTester.scala

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+/*
+ * Dummy tester to start a Chisel project.
+ *
+ * Author: Martin Schoeberl ([email protected])
+ * 
+ */
+
+package empty
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+class AddTester extends AnyFlatSpec with ChiselScalatestTester {
+
+  "Add" should "work" in {
+    test(new Add) { dut =>
+      for (a <- 0 to 2) {
+        for (b <- 0 to 3) {
+          val result = a + b
+          dut.io.a.poke(a.U)
+          dut.io.b.poke(b.U)
+          dut.clock.step(1)
+          dut.io.c.expect(result.U)
+        }
+      }
+    }
+  }
+}