IEEE754:int->IEEE754-32bit 구현

Makefile

@@ -6,18 +6,24 @@ doit:
 test:
 	sbt test
 
+# 삼각함수 관련
 LutGen:
 	python /home/jongsang/vfropeHW/src/main/scala/vfrope/LutGen.py
 
+SinCosLUT:
+	sbt "testOnly vfrope.SinCosLUTTest"
+
+#실수연산 관련
 32Ieee754:
 	python /home/jongsang/vfropeHW/src/test/scala/vfrope/32bit-ieee754.py
 
-SinCosLUT:
-	sbt "testOnly vfrope.SinCosLUTTest"
+Int32toIEEE754:
+	sbt "testOnly vfrope.Int32ToIEEE754Test"
 
 FixedPoint:
 	sbt "testOnly vfrope.CombinedTestSuite"
 
+#RoPE모듈관련
 RoPEModule_Int:
 	sbt "testOnly vfrope.RoPEModuleIntTester"
 

ropeModule.drawio

@@ -49,7 +49,7 @@
                 <mxCell id="65" value="&lt;font color=&quot;#000000&quot;&gt;i&lt;br&gt;int32&lt;/font&gt;" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#FFFFFF;" parent="1" vertex="1">
                     <mxGeometry x="120" y="440" width="120" height="40" as="geometry"/>
                 </mxCell>
-                <mxCell id="66" value="theta&lt;br&gt;FP32" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#FFFFFF;" parent="1" vertex="1">
+                <mxCell id="66" value="&lt;font color=&quot;#000000&quot;&gt;theta&lt;br&gt;FP32&lt;/font&gt;" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#FFFFFF;" parent="1" vertex="1">
                     <mxGeometry x="120" y="520" width="120" height="40" as="geometry"/>
                 </mxCell>
                 <mxCell id="67" value="x_1 reg&lt;br&gt;FP32" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
@@ -323,13 +323,8 @@
                 <mxCell id="140" style="edgeStyle=none;html=1;exitX=1;exitY=0.5;exitDx=0;exitDy=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;strokeColor=#000000;" parent="1" source="132" target="138" edge="1">
                     <mxGeometry relative="1" as="geometry"/>
                 </mxCell>
-                <mxCell id="161" value="" style="edgeStyle=none;html=1;strokeColor=#000000;fillColor=#000000;" edge="1" parent="1" target="146">
-                    <mxGeometry relative="1" as="geometry">
-                        <mxPoint x="678.0357142857142" y="100" as="sourcePoint"/>
-                    </mxGeometry>
-                </mxCell>
                 <mxCell id="154" value="&lt;div style=&quot;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&lt;font style=&quot;font-size: 24px;&quot;&gt;Stage 2&lt;/font&gt;&lt;/span&gt;&lt;/div&gt;" style="text;whiteSpace=wrap;html=1;align=center;" parent="1" vertex="1">
-                    <mxGeometry x="930" y="110" width="180" height="50" as="geometry"/>
+                    <mxGeometry x="930" y="50" width="180" height="50" as="geometry"/>
                 </mxCell>
                 <mxCell id="155" value="&lt;div style=&quot;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&lt;font style=&quot;font-size: 24px;&quot;&gt;Stage 3&lt;/font&gt;&lt;/span&gt;&lt;/div&gt;" style="text;whiteSpace=wrap;html=1;align=center;" parent="1" vertex="1">
                     <mxGeometry x="1370" y="50" width="180" height="50" as="geometry"/>
@@ -354,7 +349,7 @@
                     </mxGeometry>
                 </mxCell>
                 <mxCell id="162" value="&lt;div style=&quot;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&lt;font style=&quot;font-size: 24px;&quot;&gt;Stage 1&lt;/font&gt;&lt;/span&gt;&lt;/div&gt;" style="text;whiteSpace=wrap;html=1;align=center;" vertex="1" parent="1">
-                    <mxGeometry x="530" y="110" width="180" height="50" as="geometry"/>
+                    <mxGeometry x="530" y="50" width="180" height="50" as="geometry"/>
                 </mxCell>
             </root>
         </mxGraphModel>

src/main/scala/vfrope/ieee754.scala

@@ -0,0 +1,30 @@
+package vfrope
+
+import chisel3._
+import chisel3.util._
+
+class Int32ToIEEE754 extends Module {
+  val io = IO(new Bundle {
+    val inInt = Input(SInt(32.W))
+    val outIEEE = Output(UInt(32.W)) // IEEE 754 형식의 결과 출력
+  })
+
+  // 부호 비트 설정
+  val sign = io.inInt(31)
+  val absVal = Mux(sign === 1.U, -io.inInt, io.inInt).asUInt()
+
+  // Find the leading one position and adjust in one step
+  val LeadingOne = 31.U - PriorityEncoder(Reverse(absVal))
+
+  // Corrected normalized mantissa calculation (combined in one step)
+  val normalizedMantissa = (absVal << (23.U - LeadingOne))(22, 0) // Shift and extract 23 bits mantissa in one step
+
+  // Corrected exponent calculation (combined in one step)
+  val biasedExponent = (LeadingOne +& 127.U)(7, 0)  // Calculate biased exponent in one line
+
+  // Final IEEE 754 representation
+  val outIEEE = Cat(sign, biasedExponent, normalizedMantissa)
+
+  // Assign the result to the IO output
+  io.outIEEE := outIEEE
+}

src/test/scala/vfrope/32bit-ieee754.py

@@ -4,12 +4,16 @@ def float_to_ieee754_single_precision_hex(num):
     packed = struct.pack('>f', num)
     return ''.join(f'{byte:02x}' for byte in packed)
 
+def Uint32toIEEE754(a):
+    res = float_to_ieee754_single_precision_hex(a)
+    print("=== UINT32 to IEEE754")
+    print(a," = ",res)
 
 def FP32ADD(a,b):
     FP32_a = float_to_ieee754_single_precision_hex(a)
     FP32_b = float_to_ieee754_single_precision_hex(b)
     FP32_res = float_to_ieee754_single_precision_hex(a+b)
-    print("=== FP32 ADDER ===")
+    print("\n=== FP32 ADDER ===")
     print(f'{a} + {b} = {a+b}')
     print(f'{FP32_a} + {FP32_b} = {FP32_res}')
 
@@ -24,6 +28,7 @@ def FP32MULT(a,b):
 def main():
     a = 1.5
     b = 2.25
+    Uint32toIEEE754(-15)
     FP32ADD(a,b)
     FP32MULT(a,b)
 

src/test/scala/vfrope/ieee754test.scala

@@ -0,0 +1,15 @@
+package vfrope
+
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import chisel3._
+
+class Int32ToIEEE754Test extends AnyFlatSpec with ChiselScalatestTester {
+    "Int32ToIEEE754" should "convert integer to IEEE 754" in {
+        test(new Int32ToIEEE754()) { dut =>
+            dut.io.inInt.poke(-15.S) // 0x41700000
+            dut.clock.step()
+            println(s"Result: 0x${dut.io.outIEEE.peek().litValue.toString(16)}")
+        }
+    }
+}