Move to inclusive SPI nomenclature

k3jph · Dec 11, 2022 · 087fe4d · 087fe4d
1 parent ca24455
commit 087fe4d
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Showing 2 changed files with 18 additions and 15 deletions.
diff --git a/README.md b/README.md
@@ -7,23 +7,26 @@ Holder](https://sites.google.com/site/wayneholder/besting-ben-heck).
 
 The controller requires three pins on the ATtiny85.  The pin
 assignments can be changed in the defines, but the following shows
-the default layout.  PB5 (Pin 1) should probably be connected to Vcc
+the default layout.  PB5 (Pin 1) should probably be connected to +5V
 through a resistor in the 10k- to 30k-ohm range.
 
+In this configuration, the device assumes it is the only peripheral
+on the SPI bus.  Accordingly, there is no provision for chip select.
+This may be changed in future revisions.
+
 ## Expected Connection Diagram
 
                 +====+
-     Vcc -> PB5 |*   | Vcc
-      NC <- PB3 |    | PB2 <- CLK
-    LEDs -- PB4 |    | PB1 -- NC
-            GND |    | PB0 <- MOSI
+     +5V -> PB5 |*   | +5V
+      NC -- PB3 |    | PB2 <- SCLK
+    DOUT <- PB4 |    | PB1 -- NC
+            GND |    | PB0 <- COPI
                 +====+
 
 ## Direct Dependencies
 
-* [PlatformIO](https://platformio.org/)
-
-PlatformIO is used to manage the build environment.
+* [GCC for AVR](https://www.microchip.com/en-us/tools-resources/develop/microchip-studio/gcc-compilers) for compiling
+* [CMake](https://cmake.org/) is used to manage the build environment.
 
 ## Contribution guidelines
 

diff --git a/src/main.S b/src/main.S
@@ -26,22 +26,22 @@
 ;
 ;  The controller requires three pins on the ATtiny85.  The pin
 ;  assignments can be changed below, but the following shows the
-;  default layout.  PB5 (Pin 1) shold probably be connected to Vcc
+;  default layout.  PB5 (Pin 1) shold probably be connected to +5V
 ;  through a resistor in the 10k- to 30k-ohm range.
 ;
 ;               +====+
-;    Vcc -> PB5 |*   | Vcc
+;    +5V -> PB5 |*   | +5V
 ;     NC <- PB3 |    | PB2 <- SCLK
-;   LEDs -- PB4 |    | PB1 -- NC
-;           GND |    | PB0 <- MOSI
+;   DOUT <- PB4 |    | PB1 -- NC
+;           GND |    | PB0 <- COPI
 ;               +====+
 
 #define __SFR_OFFSET 0
 
 #include <avr/io.h>
 
 ;  Give the ports we intend to use functional names
-#define MOSI    DDB0
+#define COPI    DDB0
 #define SCLK    DDB2
 #define DOUT    DDB4
 
@@ -54,7 +54,7 @@ RESET:                      ; Reset the Attiny85
     clr     r17             ; Set Clock Prescaler to 1:1 (CLKPR = 0)
     out     CLKPR, r17
 
-    cbi     DDRB, MOSI      ; Set MOSI as input
+    cbi     DDRB, COPI      ; Set COPI as input
     cbi     DDRB, SCLK      ; Set SCLK as input
     sbi     DDRB, DOUT      ; Set DOUT as output
     cbi     PORTB, DOUT     ; Set DOUT LOW to clear the port
@@ -66,7 +66,7 @@ WAIT_SCLK_HI:               ; Wait for the next clock signal
     sbis    PINB, SCLK      ; Wait for CLK to go HIGH (rising edge)
     rjmp    WAIT_SCLK_HI
     cli                     ; Disable interrupts for RT performance
-    sbis    PINB, MOSI      ; Skip if MOSI "1" bit
+    sbis    PINB, COPI      ; Skip if COPI "1" bit
     rjmp    SEND_0          ; Send 0 to DOUT
 
 SEND_1:                     ; Else send 1 to DOUT