Update mesh and transposer skeleton

kaist-cp · Oct 28, 2024 · b0c3a70 · b0c3a70
1 parent ec821fb
commit b0c3a70
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Showing 5 changed files with 14 additions and 33 deletions.
diff --git a/hazardflow-designs/src/gemmini/execute/systolic_array/mesh.rs b/hazardflow-designs/src/gemmini/execute/systolic_array/mesh.rs
@@ -1,4 +1,5 @@
 //! Mesh.
+
 #![allow(unused)] // Added for assignment.
 
 use super::tile::*;
@@ -13,18 +14,18 @@ pub type MeshColData = [TileColData; MESH_COLS];
 /// Mesh.
 pub fn mesh<const LATENCY: usize>(in_left: MeshRowData, in_top: MeshColData) -> (MeshRowData, MeshColData)
 where [(); 1 + LATENCY]: {
-    todo!("Assignment 5")
+    todo!("assignment 5")
 }
 
 /// Debug
 #[synthesize]
 pub fn mesh_4_4(in_left: MeshRowData, in_top: MeshColData) -> (MeshRowData, MeshColData) {
-    // Only the Column data are used as output
     mesh::<1>(in_left, in_top)
 }
 
 /// Chisel Mesh Wrapper.
-/// This module allows students to proceed with future assignments even if they have not completed Assignment5.
+///
+/// This module allows students to proceed with future assignments even if they have not completed assignment 5.
 #[magic(ffi::MeshWrapper())]
 pub fn mesh_chisel(_in_left: MeshRowData, _in_top: MeshColData) -> (MeshRowData, MeshColData) {
     todo!("MeshWrapper.v")

diff --git a/hazardflow-designs/src/gemmini/execute/systolic_array/transposer.rs b/hazardflow-designs/src/gemmini/execute/systolic_array/transposer.rs
@@ -1,4 +1,5 @@
 //! Transposer.
+
 #![allow(unused)] // Added for assignment.
 
 use super::*;
@@ -18,17 +19,16 @@ impl Dir {
     }
 }
 
-/// -> (out_right, (out_bottom, dir))
-
+/// Returns `(out_right, (out_bottom, dir))`.
 fn t_pe(
     in_left: Valid<U<INPUT_BITS>>,
     (in_top, dir): (Valid<U<INPUT_BITS>>, Valid<Dir>),
 ) -> (Valid<U<INPUT_BITS>>, (Valid<U<INPUT_BITS>>, Valid<Dir>)) {
-    todo!("Assignment 5")
+    todo!("assignment 5")
 }
 
 // Helper functions to use `array_map`.
-// Currenlty, array_map does not take closure as an argument, so we need to define a helper function.
+// Currently, array_map does not take closure as an argument, so we need to define a helper function.
 fn unzip_tup_interface(i: Valid<(U<INPUT_BITS>, Dir)>) -> (Valid<U<INPUT_BITS>>, Valid<Dir>) {
     i.unzip()
 }
@@ -42,7 +42,7 @@ where
     [(); max(clog2(DIM), 1)]:,
     [(); max(clog2(DIM), 1) + 1]:,
 {
-    todo!("Assignment 5")
+    todo!("assignment 5")
 }
 
 /// Debug
@@ -52,7 +52,8 @@ pub fn transposer_default(in_row: Valid<Array<U<INPUT_BITS>, 16>>) -> Valid<Arra
 }
 
 /// Chisel Transposer Wrapper.
-/// This module allows students to proceed with future assignments even if they have not completed Assignment5.
+///
+/// This module allows students to proceed with future assignments even if they have not completed assignment 5.
 #[magic(ffi::TransposerWrapper())]
 pub fn transposer_chisel(_in_row: Valid<Array<U<INPUT_BITS>, 16>>) -> Valid<Array<U<INPUT_BITS>, 16>> {
     todo!("TransposerWrapper.v")

diff --git a/scripts/gemmini/unit_tests/mesh_4_4/test_mesh_4_4.py b/scripts/gemmini/unit_tests/mesh_4_4/test_mesh_4_4.py
@@ -50,9 +50,6 @@ def __init__(self, dut):
             self.dut.in_input_1_1_payload_Some_0_control_propagate_discriminant
         )
         self.in_col_ctrl_shift = self.dut.in_input_1_1_payload_Some_0_control_shift
-        self.in_col_ctrl_bad_dataflow = (
-            self.dut.in_input_1_1_payload_Some_0_bad_dataflow
-        )
 
         self.out_row_data_valids = self.dut.out_output_0_payload_discriminant
         self.out_row_data_a = self.dut.out_output_0_payload_Some_0_a
@@ -71,9 +68,6 @@ def __init__(self, dut):
             self.dut.out_output_1_1_payload_Some_0_control_propagate_discriminant
         )
         self.out_col_ctrl_shift = self.dut.out_output_1_1_payload_Some_0_control_shift
-        self.out_col_ctrl_bad_dataflow = (
-            self.dut.out_output_1_1_payload_Some_0_bad_dataflow
-        )
 
     async def reset(self):
         self.dut.rst.setimmediatevalue(0)
@@ -138,10 +132,8 @@ async def ws_simple(dut):
     col_ctrl_last = [False] * 16
     col_ctrl_dataflow = [WS] * 16
     col_ctrl_shift = [0] * 16
-    col_ctrl_bad_dataflow = [False] * 16
 
     tb.in_col_ctrl_valids.value = concatenate_data(col_ctrl_valids, 1)
-    tb.in_col_ctrl_bad_dataflow.value = concatenate_data(col_ctrl_bad_dataflow, 1)
     tb.in_col_ctrl_dataflow.value = concatenate_data(col_ctrl_dataflow, 1)
     tb.in_col_ctrl_id.value = concatenate_data(col_ctrl_id, 3)
     tb.in_col_ctrl_last.value = concatenate_data(col_ctrl_last, 1)
@@ -280,10 +272,8 @@ async def ws_random(dut):
     col_ctrl_last = [False] * 16
     col_ctrl_dataflow = [WS] * 16
     col_ctrl_shift = [0] * 16
-    col_ctrl_bad_dataflow = [False] * 16
 
     tb.in_col_ctrl_valids.value = concatenate_data(col_ctrl_valids, 1)
-    tb.in_col_ctrl_bad_dataflow.value = concatenate_data(col_ctrl_bad_dataflow, 1)
     tb.in_col_ctrl_dataflow.value = concatenate_data(col_ctrl_dataflow, 1)
     tb.in_col_ctrl_id.value = concatenate_data(col_ctrl_id, 3)
     tb.in_col_ctrl_last.value = concatenate_data(col_ctrl_last, 1)
@@ -421,10 +411,8 @@ async def os_simple(dut):
     col_ctrl_last = [False] * 16
     col_ctrl_dataflow = [OS] * 16
     col_ctrl_shift = [0] * 16
-    col_ctrl_bad_dataflow = [False] * 16
 
     tb.in_col_ctrl_valids.value = concatenate_data(col_ctrl_valids, 1)
-    tb.in_col_ctrl_bad_dataflow.value = concatenate_data(col_ctrl_bad_dataflow, 1)
     tb.in_col_ctrl_dataflow.value = concatenate_data(col_ctrl_dataflow, 1)
     tb.in_col_ctrl_id.value = concatenate_data(col_ctrl_id, 3)
     tb.in_col_ctrl_last.value = concatenate_data(col_ctrl_last, 1)
@@ -532,10 +520,8 @@ async def os_random(dut):
     col_ctrl_last = [False] * 16
     col_ctrl_dataflow = [OS] * 16
     col_ctrl_shift = [0] * 16
-    col_ctrl_bad_dataflow = [False] * 16
 
     tb.in_col_ctrl_valids.value = concatenate_data(col_ctrl_valids, 1)
-    tb.in_col_ctrl_bad_dataflow.value = concatenate_data(col_ctrl_bad_dataflow, 1)
     tb.in_col_ctrl_dataflow.value = concatenate_data(col_ctrl_dataflow, 1)
     tb.in_col_ctrl_id.value = concatenate_data(col_ctrl_id, 3)
     tb.in_col_ctrl_last.value = concatenate_data(col_ctrl_last, 1)

diff --git a/scripts/gemmini/verilog_wrappers/MeshBlackBox.v b/scripts/gemmini/verilog_wrappers/MeshBlackBox.v
@@ -285,7 +285,6 @@ module MeshBlackBoxAdapter (
     wire [16-1:0] in_input_1_1_payload_Some_0_control_dataflow_discriminant;
     wire [16-1:0] in_input_1_1_payload_Some_0_control_propagate_discriminant;
     wire [80-1:0] in_input_1_1_payload_Some_0_control_shift;
-    wire [16-1:0] in_input_1_1_payload_Some_0_bad_dataflow = 16'h00;
 
     wire [16-1:0] out_output_0_payload_discriminant;
     wire [128-1:0] out_output_0_payload_Some_0_a;
@@ -298,7 +297,6 @@ module MeshBlackBoxAdapter (
     wire [16-1:0] out_output_1_1_payload_Some_0_control_dataflow_discriminant;
     wire [16-1:0] out_output_1_1_payload_Some_0_control_propagate_discriminant;
     wire [80-1:0] out_output_1_1_payload_Some_0_control_shift;
-    wire [16-1:0] out_output_1_1_payload_Some_0_bad_dataflow;
 
     mesh_4_4_top mesh_4_4
     (
@@ -315,7 +313,6 @@ module MeshBlackBoxAdapter (
         .in_input_1_1_payload_Some_0_control_dataflow_discriminant(in_input_1_1_payload_Some_0_control_dataflow_discriminant),
         .in_input_1_1_payload_Some_0_control_propagate_discriminant(in_input_1_1_payload_Some_0_control_propagate_discriminant),
         .in_input_1_1_payload_Some_0_control_shift(in_input_1_1_payload_Some_0_control_shift),
-        .in_input_1_1_payload_Some_0_bad_dataflow(in_input_1_1_payload_Some_0_bad_dataflow),
         .out_output_0_payload_discriminant(out_output_0_payload_discriminant),
         .out_output_0_payload_Some_0_a(out_output_0_payload_Some_0_a),
         .out_output_1_0_payload_discriminant(out_output_1_0_payload_discriminant),
@@ -326,8 +323,7 @@ module MeshBlackBoxAdapter (
         .out_output_1_1_payload_Some_0_last(out_output_1_1_payload_Some_0_last),
         .out_output_1_1_payload_Some_0_control_dataflow_discriminant(out_output_1_1_payload_Some_0_control_dataflow_discriminant),
         .out_output_1_1_payload_Some_0_control_propagate_discriminant(out_output_1_1_payload_Some_0_control_propagate_discriminant),
-        .out_output_1_1_payload_Some_0_control_shift(out_output_1_1_payload_Some_0_control_shift),
-        .out_output_1_1_payload_Some_0_bad_dataflow(out_output_1_1_payload_Some_0_bad_dataflow)
+        .out_output_1_1_payload_Some_0_control_shift(out_output_1_1_payload_Some_0_control_shift)
     );
 
     // assign io_in_a

diff --git a/scripts/gemmini/verilog_wrappers/PE256Wrapper.v b/scripts/gemmini/verilog_wrappers/PE256Wrapper.v
@@ -12,7 +12,6 @@ module PE256Wrapper (
     input wire in_input_1_1_payload_Some_0_control_dataflow_discriminant,
     input wire in_input_1_1_payload_Some_0_control_propagate_discriminant,
     input wire [5-1:0] in_input_1_1_payload_Some_0_control_shift,
-    input wire in_input_1_1_payload_Some_0_bad_dataflow,
     output wire out_output_0_payload_discriminant,
     output wire [8-1:0] out_output_0_payload_Some_0_a,
     output wire out_output_1_0_payload_discriminant,
@@ -23,8 +22,7 @@ module PE256Wrapper (
     output wire out_output_1_1_payload_Some_0_last,
     output wire out_output_1_1_payload_Some_0_control_dataflow_discriminant,
     output wire out_output_1_1_payload_Some_0_control_propagate_discriminant,
-    output wire [5-1:0] out_output_1_1_payload_Some_0_control_shift,
-    output wire out_output_1_1_payload_Some_0_bad_dataflow
+    output wire [5-1:0] out_output_1_1_payload_Some_0_control_shift
 );
     wire io_in_valid = in_input_0_payload_discriminant || in_input_1_0_payload_discriminant;
     wire io_out_valid;
@@ -49,8 +47,7 @@ module PE256Wrapper (
         .io_out_control_shift(out_output_1_1_payload_Some_0_control_shift),
         .io_out_id(out_output_1_1_payload_Some_0_id),
         .io_out_last(out_output_1_1_payload_Some_0_last),
-        .io_out_valid(io_out_valid),
-        .io_bad_dataflow(out_output_1_1_payload_Some_0_bad_dataflow)
+        .io_out_valid(io_out_valid)
     );
 
     assign out_output_0_payload_discriminant = io_out_valid;