bsp/nucleo-f7xx: Add configuration for I2S

Settings for PLLI2S that can be used for audio. I2S clock is suitable for 48 kHz sample rate. Code also enables I2S in ST HAL config by defining HAL_I2S_MODULE_ENABLE Signed-off-by: Jerzy Kasenberg <[email protected]>
kasjer · Jan 28, 2025 · c29eaf0 · c29eaf0
1 parent 39ef94e
commit c29eaf0
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Showing 4 changed files with 25 additions and 2 deletions.
diff --git a/hw/bsp/nucleo-f746zg/include/bsp/stm32f7xx_hal_conf.h b/hw/bsp/nucleo-f746zg/include/bsp/stm32f7xx_hal_conf.h
@@ -65,7 +65,6 @@
 #define HAL_NOR_MODULE_ENABLED
 #define HAL_SDRAM_MODULE_ENABLED
 #define HAL_HASH_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
 #define HAL_IRDA_MODULE_ENABLED
 #define HAL_SMARTCARD_MODULE_ENABLED
 #define HAL_DFSDM_MODULE_ENABLED
@@ -87,6 +86,7 @@
 #define HAL_SRAM_MODULE_ENABLED
 #define HAL_GPIO_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
 #define HAL_IWDG_MODULE_ENABLED
 #define HAL_LPTIM_MODULE_ENABLED
 #define HAL_PWR_MODULE_ENABLED

diff --git a/hw/bsp/nucleo-f746zg/syscfg.yml b/hw/bsp/nucleo-f746zg/syscfg.yml
@@ -37,10 +37,21 @@ syscfg.vals:
     STM32_CLOCK_HSI: 0
     STM32_CLOCK_HSE: 1
     STM32_CLOCK_HSE_BYPASS: 1
+    # Input clock for all PLLs 8MHz / 8 = 1 MHz
     STM32_CLOCK_PLL_PLLM: 8
+    # VCO = 1MHz * 432 = 432 MHz
     STM32_CLOCK_PLL_PLLN: 432
+    # PLLP - PLLCLK = VCO / 2 = 216
     STM32_CLOCK_PLL_PLLP: 2
+    # PLLQ - PLL48CLK = VCO / 9 = 48
     STM32_CLOCK_PLL_PLLQ: 9
+    STM32_CLOCK_PLLI2S_PLLN: 384
+    # PLLI2SP - SPDIFRX = 48 MHz
+    STM32_CLOCK_PLLI2S_PLLP: 8
+    # PLLI2SQ - SAICLK = 192 MHz
+    STM32_CLOCK_PLLI2S_PLLQ: 2
+    # PLLI2SR - I2SCLK = 192 MHz
+    STM32_CLOCK_PLLI2S_PLLR: 2
     STM32_CLOCK_ENABLE_OVERDRIVE: 0
     STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
     STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV4'

diff --git a/hw/bsp/nucleo-f767zi/include/bsp/stm32f7xx_hal_conf.h b/hw/bsp/nucleo-f767zi/include/bsp/stm32f7xx_hal_conf.h
@@ -65,7 +65,6 @@
 #define HAL_NOR_MODULE_ENABLED
 #define HAL_SDRAM_MODULE_ENABLED
 #define HAL_HASH_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
 #define HAL_DFSDM_MODULE_ENABLED
 #define HAL_DSI_MODULE_ENABLED
 #define HAL_JPEG_MODULE_ENABLED
@@ -85,6 +84,7 @@
 #define HAL_SRAM_MODULE_ENABLED
 #define HAL_GPIO_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
 #define HAL_IWDG_MODULE_ENABLED
 #define HAL_LPTIM_MODULE_ENABLED
 #define HAL_PWR_MODULE_ENABLED

diff --git a/hw/bsp/nucleo-f767zi/syscfg.yml b/hw/bsp/nucleo-f767zi/syscfg.yml
@@ -37,11 +37,23 @@ syscfg.vals:
     STM32_CLOCK_HSI: 0
     STM32_CLOCK_HSE: 1
     STM32_CLOCK_HSE_BYPASS: 1
+    # Input clock for all PLLs 8MHz / 8 = 1 MHz
     STM32_CLOCK_PLL_PLLM: 8
+    # VCO = 1MHz * 432 = 432 MHz
     STM32_CLOCK_PLL_PLLN: 432
+    # PLLP - PLLCLK = VCO / 2 = 216
     STM32_CLOCK_PLL_PLLP: 2
+    # PLLQ - PLL48CLK = VCO / 9 = 48
     STM32_CLOCK_PLL_PLLQ: 9
+    # PLLR - PLLDSICLK = VCO / 7 = 30.85 MHz
     STM32_CLOCK_PLL_PLLR: 7
+    STM32_CLOCK_PLLI2S_PLLN: 384
+    # PLLI2SP - SPDIFRX = 48 MHz
+    STM32_CLOCK_PLLI2S_PLLP: 8
+    # PLLI2SQ - SAICLK = 192 MHz
+    STM32_CLOCK_PLLI2S_PLLQ: 2
+    # PLLI2SR - I2SCLK = 192 MHz
+    STM32_CLOCK_PLLI2S_PLLR: 2
     STM32_CLOCK_ENABLE_OVERDRIVE: 0
     STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
     STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV4'