arm: bsp: add ARM FVP Base-R platform

Change-Id: I6177ea73dc2893be77ca706891b2823940a23682

src/kern/arm/bsp/fvp_base_r/Kconfig

@@ -0,0 +1,5 @@
+# PF: FVP_BASE_R
+# PFDESCR: ARM FVP Base-R Platform
+# PFDEPENDS: ARM
+# PFSELECT: ARM_GIC HAVE_ARM_GICV3
+# PFSELECT: CAN_ARM_CPU_CORTEX_R52 CAN_ARM_CPU_CORTEX_R82

src/kern/arm/bsp/fvp_base_r/Modules

@@ -0,0 +1,17 @@
+# vim:set ft=make:
+
+OBJECTS_LIBUART       += uart_pl011.o
+CXXFLAGS_uart-libuart += $(call LIBUART_UART, pl011)
+PREPROCESS_PARTS      += generic_tickless_idle \
+                         arm_generic_timer pic_gic
+INTERFACES_KERNEL     += generic_timer
+RAM_PHYS_BASE         := 0x0f000000
+
+config_IMPL           += config-arm-fvp_base_r
+mem_layout_IMPL       += mem_layout-arm-fvp_base_r
+pic_IMPL              += pic-gic pic-arm-fvp_base_r
+timer_IMPL            += timer-arm-generic timer-arm-generic-fvp_base_r
+timer_tick_IMPL       += timer_tick-single-vector
+reset_IMPL            += reset-arm-fvp_base_r
+clock_IMPL            += clock-generic
+platform_control_IMPL += platform_control-arm-fvp_base_r

src/kern/arm/bsp/fvp_base_r/config-arm-fvp_base_r.cpp

@@ -0,0 +1,3 @@
+INTERFACE [arm && pf_fvp_base_r]:
+
+#define TARGET_NAME "ARM FVP Base-R platform"

src/kern/arm/bsp/fvp_base_r/mem_layout-arm-fvp_base_r.cpp

@@ -0,0 +1,17 @@
+INTERFACE [arm && pf_fvp_base_r]: //------------------------------------------
+
+EXTENSION class Mem_layout
+{
+public:
+  enum Phys_layout_s32: Address {
+    // Map whole GIC
+    Gic_phys_base     = 0xaf000000,
+    Gic_phys_size     =   0x200000,
+    Gic_redist_offset =   0x100000,
+    Gic_redist_size   =   0x100000,
+
+    // Acutally 32 regions on EL1 and EL2 but we can only handle 31 efficiently
+    // at the moment.
+    Mpu_regions = 31,
+  };
+};

src/kern/arm/bsp/fvp_base_r/pic-arm-fvp_base_r.cpp

@@ -0,0 +1,36 @@
+INTERFACE [arm && pic_gic && pf_fvp_base_r]:
+
+#include "gic.h"
+#include "initcalls.h"
+
+// ------------------------------------------------------------------------
+IMPLEMENTATION [arm && pic_gic && pf_fvp_base_r]:
+
+#include "boot_alloc.h"
+#include "gic_v3.h"
+#include "irq_mgr.h"
+#include "kmem.h"
+
+PUBLIC static FIASCO_INIT
+void
+Pic::init()
+{
+  typedef Irq_mgr_single_chip<Gic_v3> M;
+
+  auto regs = Kmem::mmio_remap(Mem_layout::Gic_phys_base,
+                               Mem_layout::Gic_phys_size);
+
+  M *m = new Boot_object<M>(regs, regs + Mem_layout::Gic_redist_offset);
+
+  gic = &m->c;
+  Irq_mgr::mgr = m;
+}
+
+// ------------------------------------------------------------------------
+IMPLEMENTATION [arm && pic_gic && pf_fvp_base_r && mp]:
+
+PUBLIC static
+void Pic::init_ap(Cpu_number cpu, bool resume)
+{
+  gic->init_ap(cpu, resume);
+}

src/kern/arm/bsp/fvp_base_r/platform_control-arm-fvp_base_r.cpp

@@ -0,0 +1,53 @@
+// ------------------------------------------------------------------------
+IMPLEMENTATION [arm && pf_fvp_base_r && mp]:
+
+#include "cpu.h"
+#include "kmem.h"
+#include "koptions.h"
+#include "mem_unit.h"
+#include "minmax.h"
+#include "mmio_register_block.h"
+#include "poll_timeout_counter.h"
+#include "spin_lock.h"
+#include "warn.h"
+#include <lock_guard.h>
+
+PUBLIC static
+void
+Platform_control::boot_ap_cpus(Address phys_tramp_mp_addr)
+{
+  enum { Max_cores = 4 };
+
+  {
+    // Other CPUs expect that it's safe to read Kmem::kdir. We will modify it
+    // when removing the core_spin_addr mapping, though. Protect ourself from
+    // the AP CPUs seeing this short mapping!
+    extern Spin_lock<Mword> _tramp_mp_spinlock;
+    auto g = lock_guard(_tramp_mp_spinlock);
+
+    Mmio_register_block s(Kmem::mmio_remap(Koptions::o()->core_spin_addr,
+                                           sizeof(Address)));
+
+    s.r<Address>(0) = phys_tramp_mp_addr;
+    Mem::dsb();
+    Mem_unit::clean_dcache(reinterpret_cast<void *>(s.get_mmio_base()));
+
+    // Remove mappings to release precious MPU regions
+    Kmem::mmio_unmap(Koptions::o()->core_spin_addr, sizeof(Address));
+  }
+
+  for (int i = 1; i < min<int>(Max_cores, Config::Max_num_cpus); ++i)
+    {
+      // Wake up other cores from WFE in the bootstrap spin-address trampoline.
+      asm volatile("sev" : : : "memory");
+      L4::Poll_timeout_counter guard(5000000);
+      while (guard.test(!Cpu::online(Cpu_number(i))))
+        {
+          Mem::barrier();
+          Proc::pause();
+        }
+
+      if (guard.timed_out())
+        WARNX(Error, "CPU%d did not show up!\n", i);
+    }
+}

src/kern/arm/bsp/fvp_base_r/reset-arm-fvp_base_r.cpp

@@ -0,0 +1,9 @@
+IMPLEMENTATION [arm && pf_fvp_base_r]:
+
+#include "infinite_loop.h"
+
+void __attribute__ ((noreturn))
+platform_reset(void)
+{
+  L4::infinite_loop();
+}

src/kern/arm/bsp/fvp_base_r/timer-arm-generic-fvp_base_r.cpp

@@ -0,0 +1,20 @@
+IMPLEMENTATION [arm_generic_timer && pf_fvp_base_r]:
+
+PUBLIC static
+unsigned Timer::irq()
+{
+  switch (Gtimer::Type)
+    {
+    case Generic_timer::Physical:   return 30;
+    case Generic_timer::Virtual:    return 27;
+    case Generic_timer::Hyp:        return 26;
+    case Generic_timer::Secure_hyp: return 20;
+    };
+}
+
+IMPLEMENT
+void Timer::bsp_init(Cpu_number)
+{
+  if (Gtimer::frequency() == 0)
+    Gtimer::frequency(100000000);
+}