Digilent Arty-A7 Playground

A playground with various modules, written in SystemVerilog, with a project setup to simplify working routines.

Installation

FPGA

1. Install Vivado 2024.2.1

Utilities

1. Install Rust:

   curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh

2. Install Verilator:

   brew install verilator

Tooling

1. Install VS Code:

   brew install --cask visual-studio-code

2. Install Slang
3. Install verible_verilog_ls:

   brew tap chipsalliance/verible
   brew install verible

4. Install the Verilog/SystemVerilog Tools plugin for VS Code and specify paths to Slang and Verible Verilog LS.

Folder Structure

A typical top-level directory layout:

.
├── arty_a7.srcs            # Constraints and specific Vivado files
├── hosts/arty-a7-tests     # Rust project to run tests
├── vsrc                    # Module source files in SystemVerilog
├── .gitignore              # Ignore files generated by Vivado
├── arty_a7.xpr             # Vivado project file
└── README.md

Running Tests

To run tests, execute the following command from the /hosts/arty-a7-tests directory:

cargo test