Adds stage tests. Lots of bug fixes

ctrlckt_and_regfile.v

@@ -171,8 +171,8 @@ endmodule
 
 module registerFile(
 	input clk, input reset, 
-	input mem_regWrite, input [2:0] mem_rn, mem_rd, input [31:0] mem_writeData,
-	input alu_regWrite, input [2:0] alu_rm, alu_rn, alu_rd, input [31:0] alu_writeData,
+	input p4_mem_regWrite, input [2:0] mem_rn, mem_rd, p4_mem_rd, input [31:0] mem_writeData,
+	input p4_alu_regWrite, input [2:0] alu_rm, alu_rn, alu_rd, p4_alu_rd, input [31:0] alu_writeData,
 
 	output [31:0] mem_reg_rn, mem_reg_rd, 
 	output [31:0] alu_reg_rm, alu_reg_rn
@@ -182,10 +182,10 @@ module registerFile(
 
 
 	wire [7:0] alu_decOut, mem_decOut;
-	decoder3to8 alu_decoder(alu_rd, alu_decOut);
-	decoder3to8 mem_decoder(mem_rd, mem_decOut);
+	decoder3to8 alu_decoder(p4_alu_rd, alu_decOut);
+	decoder3to8 mem_decoder(p4_mem_rd, mem_decOut);
 
-	registerSet rSet0( clk, reset, alu_regWrite,mem_regWrite, alu_decOut, mem_decOut, alu_writeData, mem_writeData, outR0,outR1,outR2,outR3,outR4,outR5,outR6,outR7 ); 
+	registerSet rSet0( clk, reset, p4_alu_regWrite, p4_mem_regWrite, alu_decOut, mem_decOut, alu_writeData, mem_writeData, outR0,outR1,outR2,outR3,outR4,outR5,outR6,outR7 ); 
 	// regWrite can be 1'b1 since the decoder does the work
 
 	mux8to1_32bit mux_mrn( outR0,outR1,outR2,outR3,outR4,outR5,outR6,outR7, mem_rn, mem_reg_rn );

ex.v

@@ -6,13 +6,14 @@ module EXStage(input clk, input reset, input p3_pipeline_regWrite, input EX_flus
 
 
 		input [2:0] p2_alu_rn, p2_alu_rm, p2_alu_rd, p2_mem_rn, p2_mem_rd,
-		input [31:0] p2_alu_reg_rm, p2_alu_reg_rn, p2_mem_reg_rn, p2_mem_reg_rd, 
+		input [31:0] p2_alu_reg_rm, p2_alu_reg_rn, p2_mem_reg_rn,
+		input [7:0] p2_mem_reg_rd, 
 		input [31:0] p2_alu_sextImm3, p2_mem_sextImm5,
 
 		input 		 f_mem_reg_rd_sel, 										// Forwarding mux selectors
 		input [1:0]  f_mem_reg_rn_sel, f_alu_reg_rm_sel, f_alu_reg_rn_sel,	// Do we need an extra bit for alu_reg_rm ?
 		input [31:0] f_mem_reg_rn_1, f_mem_reg_rn_2, f_mem_reg_rn_3,	// forwarding for mem_rn
-		input [31:0] f_mem_reg_rd_1,									// forwarding for mem_rd
+		input [7:0] f_mem_reg_rd_1,									// forwarding for mem_rd
 		input [31:0] f_alu_reg_rm_1, f_alu_reg_rm_2, f_alu_reg_rm_3,	// forwarding for alu_rm
 		input [31:0] f_alu_reg_rn_1, f_alu_reg_rn_2, f_alu_reg_rn_3, 	// forwarding for alu_rn
 
@@ -28,7 +29,7 @@ module EXStage(input clk, input reset, input p3_pipeline_regWrite, input EX_flus
 	mux4to1_32bit mux_mem_reg_rn( p2_mem_reg_rn, f_mem_reg_rn_1, f_mem_reg_rn_2, f_mem_reg_rn_3, f_mem_reg_rn_sel, selected_mem_reg_rn );
 
 	wire [7:0] selected_mem_reg_rd;
-	mux2to1_32bit mux_mem_reg_rd( p2_mem_reg_rd, f_mem_reg_rd_1, f_mem_reg_rd_sel, selected_mem_reg_rd );
+	mux2to1_8bit mux_mem_reg_rd( p2_mem_reg_rd, f_mem_reg_rd_1, f_mem_reg_rd_sel, selected_mem_reg_rd );
 
 	wire [31:0] mem_address;
 	adder32bit memAddressAdder(p2_mem_sextImm5, selected_mem_reg_rn, mem_address);
@@ -53,8 +54,8 @@ module EXStage(input clk, input reset, input p3_pipeline_regWrite, input EX_flus
 		clk, rest, p3_pipeline_regWrite, EX_flush,
 
 		p2_memRead, p2_memWrite, p2_alu_regWrite, p2_mem_regWrite, p2_flag_regWrite,
-		alu_rd, mem_rd,
-		mem_reg_rd, 
+		p2_alu_rd, p2_mem_rd,
+		p2_mem_reg_rd, 
 		aluOut, mem_address,
 		alu_flag_z, alu_flag_n, alu_flag_c, alu_flag_v,
 

id.v

@@ -3,7 +3,9 @@ module IDStage(
 
 		input [15:0] p1_aluInstr, p1_memInstr,
 		input p3_flag_v, p3_flag_n, // p2_isBranch, // Already declared in the pipeline output vars				// Look down
-		input p4_mem_regWrite, p4_alu_regWrite, input [31:0] p4_alu_writeData, p4_mem_writeData,
+		input p4_mem_regWrite, p4_alu_regWrite, 
+		input [2:0] p4_alu_rd, p4_mem_rd, 
+		input [31:0] p4_alu_writeData, p4_mem_writeData,
 		input p4_flag_z, p4_flag_n, p4_flag_c, p4_flag_v,
 		// Our output
 		output [2:0] p2_alu_rm, p2_alu_rn, p2_alu_rd, p2_mem_rn, p2_mem_rd, 
@@ -17,10 +19,10 @@ module IDStage(
 		// Signals
 		output p2_memRead, p2_memWrite, p2_alu_regWrite, p2_mem_regWrite, p2_flag_regWrite,
 		output p2_aluOp, p2_aluSrcB,
-		output p2_isBranch, p2_isJump, output reg [1:0] pcSrc,														// p2_isBranch is here
+		output p2_isBranch, p2_isJump, output [1:0] pcSrc,														// p2_isBranch is here
 
 		// Flush signals
-		output IF_flush, output reg ID_flush, output reg EX_flush
+		output IF_flush, output ID_flush, output EX_flush
 		// output p2_alu_undefinedInstruction, p2_mem_undefinedInstruction, 	// Deprecated
 	);
 	// ID Stage
@@ -54,7 +56,7 @@ module IDStage(
 	);
 
 	// Flag register
-	flagRegister4bit flag_register( clk, reset, 
+	flagRegister4bit flag_register( clk, reset, 1'b1,
 		p4_flag_z, p4_flag_n, p4_flag_c, p4_flag_v,
 		flag_z, flag_n, flag_c, flag_v
 	);
@@ -63,16 +65,18 @@ module IDStage(
 	wire [31:0] alu_reg_rm, alu_reg_rn, mem_reg_rn, mem_reg_rd;
 
 	registerFile rFile( clk, reset, 
-		mem_regWrite, p1_memInstr[10:8], p1_memInstr[7:5], mem_writeData,
-		alu_regWrite, p1_aluInstr[15:13], p1_aluInstr[12:10], p1_aluInstr[9:7], alu_writeData,
+
+		p4_mem_regWrite, p1_memInstr[10:8], p1_memInstr[7:5], p4_mem_rd, p4_mem_writeData,
+		p4_alu_regWrite, p1_aluInstr[15:13], p1_aluInstr[12:10], p1_aluInstr[9:7], p4_alu_rd, p4_alu_writeData,
 
 		mem_reg_rn, mem_reg_rd, 
 		alu_reg_rm, alu_reg_rn
 	);
 
 	// Sign extended mem address & Immediate data
+	wire [31:0] alu_sext3_imm, mem_sext5_memOffset;
 	signExt3to32 alu_signExt3( p1_aluInstr[15:13], alu_sext3_imm );
-	signExt5to32 mem_signExt5( p1_memInstr[15:13], mem_sext5_memOffset );
+	signExt5to32 mem_signExt5( p1_memInstr[15:11], mem_sext5_memOffset );
 
 
 	pipeline_ID_EX p2( 
@@ -86,16 +90,19 @@ module IDStage(
 		alu_sext3_imm, mem_sext5_memOffset, 			// input
 		p2_alu_sext3_imm, p2_mem_sext5_memOffset, 		// output
 
+		// Branch target address
+		mem_shiftedSext8_branchOffset,		// input
+		p2_mem_shiftedSext8_branchOffset,	// output
 
 		// signals in
-
 		memRead, memWrite, alu_regWrite, mem_regWrite, flag_regWrite,
 		aluOp, aluSrcB, 
-		isBranch, isJump, pcSrc,
+		isBranch, isJump, 
+
 		// signals out
 		p2_memRead, p2_memWrite, p2_alu_regWrite, p2_mem_regWrite, p2_flag_regWrite,
 		p2_aluOp, p2_aluSrcB,
-		p2_isBranch, p2_isJump, p2_pcSrc
+		p2_isBranch, p2_isJump
 	);
 
 endmodule

if.v

@@ -5,7 +5,8 @@ module IFStage(
 		// From other stages
 		input pcWrite, 	input [31:0] pc_branchTarget, pc_jumpTarget, 
 		input [1:0] pcSrc, // OR the two
-		output [15:0] p1_aluInstr, p1_memInstr, p1_pc_plus4
+		output [15:0] p1_aluInstr, p1_memInstr, 
+		output [31:0] p1_pc_plus4
 	);
 
 	//Moved to in
@@ -21,12 +22,13 @@ module IFStage(
 	adder32bit adder_pc( pc_out, 32'd4 , pc_plus4 );
 
 
-	mux4to1_32bit mux_pc_writeData( pc_plus4, pc_branchTarget,  pc_jumpTarget, EXCEPTION_HANDLER_ADDRESS, pcSrc, pc_writeData );
+	mux4to1_32bit mux_pc_writeData( pc_plus4, pc_branchTarget,  pc_jumpTarget, 32'b00000000_11111111_00000000_11111111, pcSrc, pc_writeData );
 
 
 	// Instruction memory
 	wire [31:0] instr2Word;
 	wire instrMem_hit;
+
 	instructionMem instructionMemory(clk, reset, pc_out, 32'b0, instrMem_hit, instr2Word);
 
 	// P1

main.v

@@ -19,11 +19,12 @@ module mainModule(input clk, input reset);
 
 
 	// IF Related
-	wire [15:0] p1_alu_instr, p1_mem_instr; // Leaving p1
+	wire [15:0] p1_aluInstr, p1_memInstr; // Leaving p1
 	wire [31:0] p1_pc_plus4;
-	IFStage(
+	IFStage the_IFStage(
 		clk, reset, p1_pipeline_regWrite, IF_flush, 
-		pcWrite, 	p2_pc_branchTarget, pc_jumpTarget, pcSrc, // From other stages
+		pcWrite, 	p2_pc_branchTarget, pc_jumpTarget, 
+		pcSrc, // From other stages
 		p1_aluInstr, p1_memInstr, p1_pc_plus4
 	);
 
@@ -44,7 +45,7 @@ module mainModule(input clk, input reset);
 	wire [2:0] p4_alu_rd, p4_mem_rd;
 
 	// Major data flow
-	wire [31:0] p2_alu_reg_rm, p2_alu_reg_rn, p2_mem_reg_rn, p2_mem_reg_rd;
+	wire [31:0] p2_alu_reg_rm, p2_alu_reg_rn, p2_mem_reg_rn, p2_mem_reg_rd; // Shrinking p2_mem_rd in EX instantiation
 	wire [31:0] p2_alu_imm, p2_memOffset;
 	// wire [31:0] p2_pc_branchTarget, pc_jumpTarget; 			// Declared above near IF stage
 
@@ -56,10 +57,10 @@ module mainModule(input clk, input reset);
 
 	// Forwarded data flow
 	wire [31:0] f_mem_reg_rn_1, f_mem_reg_rn_2, f_mem_reg_rn_3;	// forwarding for mem_rn
-	wire [31:0] f_mem_reg_rd_1;									// forwarding for mem_rd
+	wire [7:0] f_mem_reg_rd_1;									// forwarding for mem_rd
 	wire [31:0] f_alu_reg_rm_1, f_alu_reg_rm_2, f_alu_reg_rm_3;	// forwarding for alu_rm
 	wire [31:0] f_alu_reg_rn_1, f_alu_reg_rn_2, f_alu_reg_rn_3; 	// forwarding for alu_rn
-	wire [31:0] f_memStage_mem_reg_rd;	
+	wire [7:0] f_memStage_mem_reg_rd;	
 
 
 	//  Flag register related
@@ -71,12 +72,14 @@ module mainModule(input clk, input reset);
 
 
 
-	IDStage(
+	IDStage theIDStage(
 		clk, reset, p2_pipeline_regWrite, p2_pipeline_stall, // ID_Flush is generated here itself, but p2_stall isn't
 
 		p1_aluInstr, p1_memInstr,
 		p3_flag_v, p3_flag_n, // p2_isBranch, // Already declared in the pipeline output vars				// Look down
-		p4_mem_regWrite, p4_alu_regWrite, p4_alu_aluOut, p4_mem_memOut,
+		p4_mem_regWrite, p4_alu_regWrite,
+		p4_alu_rd, p4_mem_rd,  
+		p4_alu_aluOut, p4_mem_memOut,
 		p4_flag_z, p4_flag_n, p4_flag_c, p4_flag_v,
 		// Our output
 		p2_alu_rm, p2_alu_rn, p2_alu_rd, p2_mem_rn, p2_mem_rd, 
@@ -99,14 +102,15 @@ module mainModule(input clk, input reset);
 	);
 
 
-	EXStage(clk, reset, p3_pipeline_regWrite, EX_flush,
+	EXStage theEXStage(clk, reset, p3_pipeline_regWrite, EX_flush,
 
 		p2_memRead, p2_memWrite, p2_alu_regWrite, p2_mem_regWrite, p2_flag_regWrite,
 		p2_aluOp, p2_aluSrcB, 
 		// p2_isBranch, p2_isJump, // Not needed
 
 		p2_alu_rn, p2_alu_rm, p2_alu_rd, p2_mem_rn, p2_mem_rd,
-		p2_alu_reg_rm, p2_alu_reg_rn, p2_mem_reg_rn, p2_mem_reg_rd, 
+		p2_alu_reg_rm, p2_alu_reg_rn, p2_mem_reg_rn, 
+		p2_mem_reg_rd[7:0],  									// Shrinking it here
 		p2_alu_imm, p2_memOffset, 
 
 		f_mem_reg_rd_sel, 										// Forwarding mux selectors
@@ -126,18 +130,20 @@ module mainModule(input clk, input reset);
 
 
 	// MEM stage
-	MEMStage( 
-		clk, reset,
+	MEMStage theMEMStage( 
+		clk, reset, 1'b1,
 
+		p3_alu_regWrite, p3_mem_regWrite,
 		p3_alu_rd, p3_mem_rd,
 		p3_mem_reg_rd, 
 		p3_alu_aluOut, p3_mem_address,
 
 		f_memStage_mem_rd_sel,
-		f_memStage_mem_reg_rd,
+		f_memStage_mem_reg_rd[7:0],
 
 		p3_flag_z, p3_flag_n, p3_flag_c, p3_flag_v,
 
+		p4_alu_regWrite, p4_mem_regWrite,
 		p4_alu_rd, p4_mem_rd,
 		p4_alu_aluOut,
 		p4_mem_memOut,
@@ -147,7 +153,7 @@ module mainModule(input clk, input reset);
 
 
 	// Forwarding unit
-	forwarding_unit(
+	forwarding_unit the_forwarding_unit(
 		p3_alu_regWrite, p4_alu_regWrite, p4_mem_regWrite, p2_alu_regWrite,
 		// input [4:0] p1_aluOpcode,input [4:0] p1_memOpcode,  input [4:0] p2_aluOpcode,input [4:0] p2_memOpcode, // Not needed
 		p4_mem_rd, p4_alu_rd, 
@@ -159,7 +165,7 @@ module mainModule(input clk, input reset);
 	); 	
 
 	// Hazard detection;	
-	 hazard_detection(
+	 hazard_detection the_hazard_detection(
 		p3_mem_regWrite, p3_mem_rd,
 		p2_alu_rm, p2_alu_rn, p2_mem_rn,
 		pcWrite, p1_pipeline_regWrite, p2_pipeline_stall

mem.v

@@ -1,36 +1,41 @@
 module MEMStage( 
-		input clk, reset,
+		input clk, reset, p4_pipeline_regWrite, 
 
+		input p3_alu_regWrite, p3_mem_regWrite,
 		input [2:0] p3_alu_rd, p3_mem_rd,
 		input [7:0] p3_mem_reg_rd, 
 		input [31:0] p3_alu_aluOut, p3_mem_address,
 
 		input f_memStage_mem_rd_sel,
-		input [31:0] f_memStage_mem_reg_rd,
+		input [7:0] f_memStage_mem_reg_rd,
 
 		input p3_flag_z, p3_flag_n, p3_flag_c, p3_flag_v,
 
+		output p4_alu_regWrite, p4_mem_regWrite,
 		output [2:0] p4_alu_rd, p4_mem_rd,
 		output [31:0] p4_alu_aluOut, 
 		output [31:0] p4_mem_memOut,
 		output p4_flag_z, p4_flag_n, p4_flag_c, p4_flag_v
 
 );
 
-	wire [31:0] selected_mem_rd;
-	mux2to1_32bit( p3_mem_reg_rd, f_memStage_mem_reg_rd, f_memStage_mem_rd_sel, selected_mem_rd );
+	wire [7:0] selected_mem_rd;
+	mux2to1_8bit mux_f_memStage_mem_rd( p3_mem_reg_rd, f_memStage_mem_reg_rd, f_memStage_mem_rd_sel, selected_mem_rd );
 
-	wire [7:0] mem_memOut;
-	wire [31:0] mem_memOut_zeroExt;
-	dataMem dataMemory( clk, reset, p3_mem_address, selected_mem_rd, hit, mem_memOut );
-	zeroExt8to32( mem_memOut, mem_memOut_zeroExt );
+	wire [7:0] mem_memOut_8bit;
+	wire [31:0] mem_memOut;
+	dataMem dataMemory( clk, reset, p3_mem_address, selected_mem_rd, hit, mem_memOut_8bit );
+	zeroExt8to32 zExt_memOut( mem_memOut_8bit, mem_memOut );
 
+
 	pipeline_MEM_WB p4( 
-		clk, reset,
+		clk, reset, p4_pipeline_regWrite, 
+		p3_alu_regWrite, p3_mem_regWrite,
 		p3_alu_rd, p3_mem_rd,
 		p3_alu_aluOut, mem_memOut,
 		p3_flag_z, p3_flag_n, p3_flag_c, p3_flag_v,
 
+		p4_alu_regWrite, p4_mem_regWrite,
 		p4_alu_rd, p4_mem_rd,
 		p4_alu_aluOut, p4_mem_memOut,
 		p4_flag_z, p4_flag_n, p4_flag_c, p4_flag_v