Scheduler initialization

projects/tutorial.04.timing-cap/Makefile

@@ -0,0 +1,43 @@
+.POSIX:
+
+export PLATFORM   ?=qemu_virt4
+export ROOT       :=${abspath ../..}
+export BUILD      :=${abspath build/${PLATFORM}}
+export S3K_CONF_H :=${abspath s3k_conf.h}
+
+include ${ROOT}/tools.mk
+
+APPS=app0 app1
+
+ELFS:=${patsubst %, ${BUILD}/%.elf, kernel ${APPS}}
+
+all: kernel ${APPS}
+
+clean:
+	rm -rf ${BUILD}
+
+common:
+	@${MAKE} -C ${ROOT}/common
+
+kernel: common
+	@${MAKE} -C ${ROOT}/kernel
+
+${APPS}: common
+	@${MAKE} -f ../build.mk PROGRAM=$@
+
+qemu: kernel ${APPS}
+	@ELFS="${ELFS}" ${ROOT}/scripts/qemu.sh
+
+qemu-gdb: kernel ${APPS}
+	@ELFS="${ELFS}" ${ROOT}/scripts/qemu.sh -gdb tcp::3333 -S
+
+gdb: kernel ${APPS}
+	@ELFS="${ELFS}" ${ROOT}/scripts/gdb.sh
+
+gdb-openocd: kernel ${APPS}
+	@ELFS="${ELFS}" ${ROOT}/scripts/gdb-openocd.sh
+
+size: ${ELFS}
+	${SIZE} ${ELFS}
+
+.PHONY: all clean size qemu qemu-gdb gdb kernel common ${APPS}

projects/tutorial.04.timing-cap/app0.ld

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+MEMORY {
+	RAM (rwx) : ORIGIN = 0x80010000, LENGTH = 0x10000
+}
+
+__stack_size = 1024;

projects/tutorial.04.timing-cap/app0/main.c

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+#include "altc/altio.h"
+#include "s3k/s3k.h"
+
+#define APP0_PID 0
+#define APP1_PID 1
+
+// See plat_conf.h
+#define BOOT_PMP 0
+#define RAM_MEM 1
+#define UART_MEM 2
+#define TIME_MEM 3
+#define HART0_TIME 4
+#define HART1_TIME 5
+#define HART2_TIME 6
+#define HART3_TIME 7
+#define MONITOR 8
+#define CHANNEL 9
+
+#define CAP_UART 10
+#define CAP_TMP	 11
+
+#define APP_1_BASE_ADDR 0x80020000
+#define APP_1_SIZE 0x10000
+#define APP_1_PMP_MEM 0
+#define APP_1_PMP_UART 1
+#define APP_1_TIME 2
+
+#define NO_APP_1 	0
+#define NO_APP_0 	1
+#define ROUND_ROBIN 2
+#define PARALLEL	3
+
+#define SCHEDULING NO_APP_0
+
+void setup_uart(uint64_t uart_idx)
+{
+	uint64_t uart_addr = s3k_napot_encode(UART0_BASE_ADDR, 0x8);
+	// Derive a PMP capability for accessing UART
+	s3k_cap_derive(UART_MEM, uart_idx, s3k_mk_pmp(uart_addr, S3K_MEM_RW));
+	// Load the derive PMP capability to PMP configuration
+	s3k_pmp_load(uart_idx, 1);
+	// Synchronize PMP unit (hardware) with PMP configuration
+	// false => not full synchronization.
+	s3k_sync_mem();
+}
+
+void setup_app_1(uint64_t tmp)
+{
+	uint64_t uart_addr = s3k_napot_encode(UART0_BASE_ADDR, 0x8);
+	uint64_t app1_addr = s3k_napot_encode(APP_1_BASE_ADDR, APP_1_SIZE);
+
+	// Derive a PMP capability for app1 main memory
+	alt_printf("1 %X\n",
+		s3k_cap_derive(RAM_MEM, tmp, s3k_mk_pmp(app1_addr, S3K_MEM_RWX))
+			   );
+	alt_printf("2 %X\n",
+			   s3k_mon_cap_move(MONITOR, APP0_PID, tmp, APP1_PID, APP_1_PMP_MEM)
+			   );
+	alt_printf("3 %X\n",
+			   s3k_mon_pmp_load(MONITOR, APP1_PID, APP_1_PMP_MEM, 0)
+			   );
+
+	// Derive a PMP capability for uart
+	alt_printf("4 %X\n",
+			   s3k_cap_derive(UART_MEM, tmp, s3k_mk_pmp(uart_addr, S3K_MEM_RW))
+			   );
+
+	alt_printf("5 %X\n",
+			   s3k_mon_cap_move(MONITOR, APP0_PID, tmp, APP1_PID, APP_1_PMP_UART)
+			   );
+	alt_printf("6 %X\n",
+			   s3k_mon_pmp_load(MONITOR, APP1_PID, APP_1_PMP_UART, 1)
+			   );
+
+	// Write start PC of app1 to PC
+	alt_printf("9 %X\n",
+			   s3k_mon_reg_write(MONITOR, APP1_PID, S3K_REG_PC, APP_1_BASE_ADDR)
+			   );
+
+	s3k_sync_mem();
+}
+
+void setup_scheduling(uint64_t tmp_cap_idx) {
+	// Disable the other two cores
+	s3k_cap_delete(HART2_TIME);
+	s3k_cap_delete(HART3_TIME);
+
+	if (SCHEDULING == NO_APP_1) {
+		s3k_cap_delete(HART1_TIME);
+	} 
+	else if (SCHEDULING == NO_APP_0) {
+		// Notice that we must be able to finish our job to setup APP 1
+		s3k_cap_delete(HART1_TIME);
+		s3k_cap_derive(HART0_TIME, tmp_cap_idx, s3k_mk_time(S3K_MIN_HART, 0, S3K_SLOT_CNT / 2));
+		s3k_mon_cap_move(MONITOR, APP0_PID, HART0_TIME, APP1_PID, APP_1_TIME);
+	}
+	else if (SCHEDULING == ROUND_ROBIN) {
+		s3k_cap_delete(HART1_TIME);
+		alt_printf("Time derivation %d \n", 
+			s3k_cap_derive(HART0_TIME, tmp_cap_idx, s3k_mk_time(S3K_MIN_HART, 0, 
+												 S3K_SLOT_CNT / 2)));
+		alt_printf("Time delegation %d \n", 
+			s3k_mon_cap_move(MONITOR, APP0_PID, tmp_cap_idx, APP1_PID, APP_1_TIME));
+	}
+	else if (SCHEDULING == PARALLEL) {
+		s3k_mon_cap_move(MONITOR, APP0_PID, HART1_TIME, APP1_PID, APP_1_TIME);
+	}
+}
+
+int main(void)
+{
+	// Setup UART access
+	setup_uart(CAP_UART);
+
+	// Setup app1 capabilities and PC
+	setup_app_1(CAP_TMP);
+
+	// Write hello world.
+	alt_puts("hello, world from app0");
+
+	// Setup scehduling
+	setup_scheduling(CAP_TMP);
+
+	// Start app1
+	alt_printf("10 %X\n", 
+			   s3k_mon_resume(MONITOR, APP1_PID) 
+			   ); 
+
+	s3k_sync();
+
+	while (1)
+		alt_puts("0");
+
+
+	// BYE!
+	alt_puts("bye from app0");
+}

projects/tutorial.04.timing-cap/app1.ld

@@ -0,0 +1,5 @@
+MEMORY {
+	RAM (rwx) : ORIGIN = 0x80020000, LENGTH = 0x10000
+}
+
+__stack_size = 1024;

projects/tutorial.04.timing-cap/app1/main.c

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+#include "altc/altio.h"
+#include "s3k/s3k.h"
+
+#define APP_1_TIME 2
+
+int main(void)
+{
+	alt_puts("hello, world from app1");
+	s3k_cap_revoke(APP_1_TIME);
+	while(1)
+			alt_puts("1");
+	alt_puts("bye from app1");
+}

projects/tutorial.04.timing-cap/build.mk

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+.POSIX:
+
+BUILD   ?=build
+PROGRAM ?=a
+
+include ${ROOT}/tools.mk
+include ${ROOT}/common/plat/${PLATFORM}.mk
+
+C_SRCS:=${wildcard ${PROGRAM}/*.c}
+S_SRCS:=${wildcard ${PROGRAM}/*.S}
+OBJS  :=${patsubst %.c,${BUILD}/%.o,${C_SRCS}} \
+	${patsubst %.S,${BUILD}/%.o,${S_SRCS}} \
+	${STARTFILES}/start.o
+DEPS  :=${OBJS:.o=.d}
+
+CFLAGS:=-march=${ARCH} -mabi=${ABI} -mcmodel=${CMODEL} \
+	-DPLATFORM_${PLATFORM} \
+	-nostdlib \
+	-Os -g3 -flto \
+	-I${COMMON_INC} -include ${S3K_CONF_H}
+
+LDFLAGS:=-march=${ARCH} -mabi=${ABI} -mcmodel=${CMODEL} \
+	 -nostdlib \
+	 -flto \
+	 -T${PROGRAM}.ld -Tdefault.ld \
+	 -Wl,--no-warn-rwx-segments \
+	 -L${COMMON_LIB} -ls3k -laltc -lplat \
+
+ELF:=${BUILD}/${PROGRAM}.elf
+BIN:=${ELF:.elf=.bin}
+HEX:=${ELF:.elf=.hex}
+DA :=${ELF:.elf=.da}
+
+all: ${ELF} ${BIN} ${HEX} ${DA}
+
+clean:
+	rm -f ${ELF} ${OBJS} ${DEPS}
+
+${BUILD}/${PROGRAM}/%.o: ${PROGRAM}/%.S
+	@mkdir -p ${@D}
+	${CC} -o $@ $< ${CFLAGS} ${INC} -MMD -c
+
+${BUILD}/${PROGRAM}/%.o: ${PROGRAM}/%.c
+	@mkdir -p ${@D}
+	${CC} -o $@ $< ${CFLAGS} ${INC} -MMD -c
+
+%.elf: ${OBJS}
+	@mkdir -p ${@D}
+	${CC} -o $@ ${OBJS} ${LDFLAGS} ${INC}
+
+%.bin: %.elf
+	${OBJCOPY} -O binary $< $@
+
+%.hex: %.elf
+	${OBJCOPY} -O ihex $< $@
+
+%.da: %.elf
+	${OBJDUMP} -D $< > $@
+
+.PHONY: all clean
+
+-include ${DEPS}

projects/tutorial.04.timing-cap/default.ld

@@ -0,0 +1,35 @@
+/* See LICENSE file for copyright and license details. */
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+
+__global_pointer$ = MIN(_sdata + 0x800, MAX(_data + 0x800, _end - 0x800));
+
+SECTIONS {
+	.text : {
+		*( .init )
+		*( .text .text.* )
+	} > RAM
+
+	.data : {
+		_data = . ;
+		*( .data )
+		*( .data.* )
+		_sdata = . ;
+		*( .sdata )
+		*( .sdata.* )
+	} > RAM
+
+	.bss : {
+		_bss = .;
+		_sbss = .;
+		*(.sbss .sbss.*)
+		*(.bss .bss.*)
+		_end = .;
+	} > RAM
+
+	.stack : ALIGN(8) {
+		. += __stack_size;
+		__stack_pointer = .;
+		_end = .;
+	}
+}

projects/tutorial.04.timing-cap/s3k_conf.h

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+#pragma once
+
+#define PLATFORM_VIRT
+#include "plat/config.h"
+
+// Number of user processes
+#define S3K_PROC_CNT 2
+
+// Number of capabilities per process.
+#define S3K_CAP_CNT 32
+
+// Number of IPC channels.
+#define S3K_CHAN_CNT 2
+
+// Number of slots per period
+#define S3K_SLOT_CNT 32ull
+
+// Length of slots in ticks.
+#define S3K_SLOT_LEN (S3K_RTC_HZ / S3K_SLOT_CNT / 100ull)
+
+// Scheduler time
+#define S3K_SCHED_TIME (S3K_SLOT_LEN / 10)
+
+// If debugging, comment
+#define NDEBUG
+#define INSTRUMENT