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Reorganize kernel to be more independent of userland
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Henrik Karlsson
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Oct 15, 2023
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,38 @@ | ||
| #pragma once | ||
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| #include <stdint.h> | ||
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| /** Get the RT clock */ | ||
| static inline uint64_t time_get(void); | ||
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| /** Set the RT clock */ | ||
| static inline void time_set(uint64_t time); | ||
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| /** Get the RT clock timeout for hart `hartid' */ | ||
| static inline uint64_t timer_get(uint64_t hartid); | ||
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| /** Set the RT clock timeout for hart `hartid' */ | ||
| static inline void timer_set(uint64_t hartid, uint64_t timeout); | ||
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| static volatile uint64_t *const MTIME = (uint64_t *)MTIME_BASE_ADDR; | ||
| static volatile uint64_t *const MTIMECMP = (uint64_t *)MTIMECMP_BASE_ADDR; | ||
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| uint64_t time_get(void) | ||
| { | ||
| return MTIME[0]; | ||
| } | ||
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| void time_set(uint64_t time) | ||
| { | ||
| MTIME[0] = time; | ||
| } | ||
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| uint64_t timer_get(uint64_t hartid) | ||
| { | ||
| return MTIMECMP[hartid]; | ||
| } | ||
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| void timer_set(uint64_t hartid, uint64_t timeout) | ||
| { | ||
| MTIMECMP[hartid] = timeout; | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,140 @@ | ||
| #pragma once | ||
| #include <stddef.h> | ||
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| /* Initializes UART */ | ||
| static inline void uart_init(void); | ||
| /* Puts one character in UART */ | ||
| static inline int uart_putc(char c); | ||
| /* Gets one character from UART */ | ||
| static inline int uart_getc(void); | ||
| /* Puts a string to UART */ | ||
| static inline int uart_write(const char *s, int size); | ||
| /* Gets a NUL terminated string */ | ||
| static inline int uart_read(char *s, int size); | ||
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| #if defined(UART_NS16550A) | ||
| /* Driver for ns16550a UART. */ | ||
| struct uart { | ||
| union { | ||
| char rbr; // Receiver buffer register (read only) | ||
| char thr; // Transmitter holding register (write only) | ||
| }; | ||
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| char ier; // Interrupt enabler register | ||
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| union { | ||
| char iir; // Interrupt identification register (read only) | ||
| char fcr; // FIFO control register (write only) | ||
| }; | ||
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| char lcr; // Line control register | ||
| char __padding; | ||
| char lsr; // Line status register | ||
| }; | ||
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| static volatile struct uart *UART0 = (volatile struct uart *)UART0_BASE_ADDR; | ||
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| // Line status register flags | ||
| #define LSR_RX_READY 0x1 // Receive data ready | ||
| #define LSR_TX_READY 0x60 // Transmit data ready | ||
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| void uart_init(void) | ||
| { | ||
| UART0->lcr = 0x3; | ||
| UART0->fcr = 0x1; | ||
| } | ||
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| int uart_putc(char c) | ||
| { | ||
| while (!(UART0->lsr & LSR_TX_READY)) | ||
| ; | ||
| UART0->thr = (unsigned char)c; | ||
| return (unsigned char)c; | ||
| } | ||
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| int uart_getc(void) | ||
| { | ||
| while (!(UART0->lsr & LSR_RX_READY)) | ||
| ; | ||
| return UART0->rbr; | ||
| } | ||
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| #elif defined(UART_SIFIVE) | ||
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| /* Driver for SiFive's UART */ | ||
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| struct uart { | ||
| int txdata; // Transmit data register | ||
| int rxdata; // Receive data register | ||
| int txctrl; // Transmit control register | ||
| int rxctrl; // Receive control register | ||
| int ie; // UART interrupt enable | ||
| int ip; // UART interrupt pending | ||
| int div; // Baud rate divisor | ||
| }; | ||
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| static volatile struct uart *const UART0 | ||
| = (volatile struct uart *)UART0_BASE_ADDR; | ||
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| // Bit masks for transmit and receive adata registers | ||
| #define TXDATA_FULL 0x80000000ul | ||
| #define RXDATA_EMPTY 0x80000000ul | ||
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| // Control register flags for enabling transmission and reception | ||
| #define TXCTRL_TXEN 0x1ul | ||
| #define RXCTRL_RXEN 0x1ul | ||
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| // Control register flags for setting stop bits | ||
| #define TXCTRL_NSTOP 0x2ul | ||
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| void uart_init(void) | ||
| { | ||
| UART0->txctrl = TXCTRL_TXEN; // Enable transmit data | ||
| UART0->rxctrl = RXCTRL_RXEN; // Enable receive data | ||
| } | ||
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| int uart_putc(char c) | ||
| { | ||
| while (UART0->txdata & TXDATA_FULL) { | ||
| } | ||
| UART0->txdata = (unsigned char)c; | ||
| return (unsigned char)c; | ||
| } | ||
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| int uart_getc(void) | ||
| { | ||
| int c; | ||
| do { | ||
| c = UART0->rxdata; | ||
| } while (c & RXDATA_EMPTY); | ||
| return c; | ||
| } | ||
| #else | ||
| #error "Missing UART" | ||
| #endif | ||
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| int uart_write(const char *s, int size) | ||
| { | ||
| if (s == NULL) | ||
| return 0; | ||
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| int i = 0; | ||
| for (i = 0; i < size && s[i] != '\0'; i++) | ||
| uart_putc(s[i]); | ||
| return i; | ||
| } | ||
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| int uart_read(char *s, int size) | ||
| { | ||
| if (s == NULL || size <= 0) | ||
| return 0; | ||
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| int i; | ||
| for (i = 0; i < size - 1; ++i) { | ||
| s[i] = uart_getc(); | ||
| if (s[i] == '\n' || s[i] == '\r') | ||
| break; | ||
| } | ||
| s[i] = '\0'; | ||
| return i; | ||
| } |
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