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generic: 6.6: mtk_eth_soc: increase QDMA RESV_BUF size
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Increase QDMA RESV_BUF from 2K to 3K for netsys v2 to match Mediatek SDK.
This helps reduce the possibility of Ethernet transmit timeouts.

Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/19d8456c3051e5f6dabf42fa770916a2126ea4bf
Signed-off-by: Daniel Golle <[email protected]>
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dangowrt committed Sep 20, 2024
1 parent 0787d95 commit 852ed03
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44 changes: 44 additions & 0 deletions target/linux/generic/pending-6.6/734-net-ethernet-mediatek-enlarge-DMA-reserve-buffer.patch
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Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
From: Chad Monroe <[email protected]>
Date: Mon, 16 Sep 2024 19:29:03 -0700
Subject: [PATCH] net: ethernet: mediatek: increase QDMA RESV_BUF size

Increase QDMA RESV_BUF from 2K to 3K for netsys v2 to match Mediatek SDK[1].
This helps reduce the possibility of Ethernet transmit timeouts.

[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/19d8456c3051e5f6dabf42fa770916a2126ea4bf

Signed-off-by: Chad Monroe <[email protected]>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 6 ++++--
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)

--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -271,6 +271,7 @@
#define MTK_WCOMP_EN BIT(24)
#define MTK_RESV_BUF (0x80 << 16)
#define MTK_MUTLI_CNT (0x4 << 12)
+#define MTK_RESV_BUF_MASK (0xff << 16)
#define MTK_LEAKY_BUCKET_EN BIT(11)

/* QDMA Flow Control Register */
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3309,12 +3309,14 @@ static int mtk_start_dma(struct mtk_eth
MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;

- if (mtk_is_netsys_v2_or_greater(eth))
+ if (mtk_is_netsys_v2_or_greater(eth)) {
+ val &= ~MTK_RESV_BUF_MASK;
val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
- else
+ } else {
val |= MTK_RX_BT_32DWORDS;
+ }
mtk_w32(eth, val, reg_map->qdma.glo_cfg);

mtk_w32(eth,
54 changes: 27 additions & 27 deletions .../linux/generic/pending-6.6/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
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Original file line number Diff line number Diff line change
Expand Up @@ -490,7 +490,7 @@ Signed-off-by: Daniel Golle <[email protected]>
.mac_finish = mtk_mac_finish,
.mac_link_down = mtk_mac_link_down,
.mac_link_up = mtk_mac_link_up,
@@ -3415,6 +3556,9 @@ static int mtk_open(struct net_device *d
@@ -3417,6 +3558,9 @@ static int mtk_open(struct net_device *d

ppe_num = eth->soc->ppe_num;

Expand All @@ -500,7 +500,7 @@ Signed-off-by: Daniel Golle <[email protected]>
err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
if (err) {
netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
@@ -3565,6 +3709,9 @@ static int mtk_stop(struct net_device *d
@@ -3567,6 +3711,9 @@ static int mtk_stop(struct net_device *d
for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
mtk_ppe_stop(eth->ppe[i]);

Expand All @@ -510,15 +510,15 @@ Signed-off-by: Daniel Golle <[email protected]>
return 0;
}

@@ -4578,6 +4725,7 @@ static const struct net_device_ops mtk_n
@@ -4580,6 +4727,7 @@ static const struct net_device_ops mtk_n
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
{
const __be32 *_id = of_get_property(np, "reg", NULL);
+ struct device_node *pcs_np;
phy_interface_t phy_mode;
struct phylink *phylink;
struct mtk_mac *mac;
@@ -4614,16 +4762,41 @@ static int mtk_add_mac(struct mtk_eth *e
@@ -4616,16 +4764,41 @@ static int mtk_add_mac(struct mtk_eth *e
mac->id = id;
mac->hw = eth;
mac->of_node = np;
Expand Down Expand Up @@ -568,7 +568,7 @@ Signed-off-by: Daniel Golle <[email protected]>
}

memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
@@ -4706,8 +4879,21 @@ static int mtk_add_mac(struct mtk_eth *e
@@ -4708,8 +4881,21 @@ static int mtk_add_mac(struct mtk_eth *e
phy_interface_zero(mac->phylink_config.supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
mac->phylink_config.supported_interfaces);
Expand All @@ -590,7 +590,7 @@ Signed-off-by: Daniel Golle <[email protected]>
phylink = phylink_create(&mac->phylink_config,
of_fwnode_handle(mac->of_node),
phy_mode, &mtk_phylink_ops);
@@ -4758,6 +4944,26 @@ free_netdev:
@@ -4760,6 +4946,26 @@ free_netdev:
return err;
}

Expand All @@ -617,7 +617,7 @@ Signed-off-by: Daniel Golle <[email protected]>
void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
{
struct net_device *dev, *tmp;
@@ -4904,7 +5110,8 @@ static int mtk_probe(struct platform_dev
@@ -4906,7 +5112,8 @@ static int mtk_probe(struct platform_dev
regmap_write(cci, 0, 3);
}

Expand All @@ -627,7 +627,7 @@ Signed-off-by: Daniel Golle <[email protected]>
err = mtk_sgmii_init(eth);

if (err)
@@ -5015,6 +5222,24 @@ static int mtk_probe(struct platform_dev
@@ -5017,6 +5224,24 @@ static int mtk_probe(struct platform_dev
}
}

Expand All @@ -652,7 +652,7 @@ Signed-off-by: Daniel Golle <[email protected]>
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
err = devm_request_irq(eth->dev, eth->irq[0],
mtk_handle_irq, 0,
@@ -5118,6 +5343,11 @@ static int mtk_remove(struct platform_de
@@ -5120,6 +5345,11 @@ static int mtk_remove(struct platform_de
mtk_stop(eth->netdev[i]);
mac = netdev_priv(eth->netdev[i]);
phylink_disconnect_phy(mac->phylink);
Expand All @@ -674,7 +674,7 @@ Signed-off-by: Daniel Golle <[email protected]>
#include <linux/rhashtable.h>
#include <linux/dim.h>
#include <linux/bitfield.h>
@@ -504,6 +505,21 @@
@@ -505,6 +506,21 @@
#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
#define INTF_MODE_RGMII_10_100 0

Expand All @@ -696,15 +696,15 @@ Signed-off-by: Daniel Golle <[email protected]>
/* GPIO port control registers for GMAC 2*/
#define GPIO_OD33_CTRL8 0x4c0
#define GPIO_BIAS_CTRL 0xed0
@@ -529,6 +545,7 @@
@@ -530,6 +546,7 @@
#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
+#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)


/* ethernet subsystem clock register */
@@ -567,6 +584,11 @@
@@ -568,6 +585,11 @@
#define GEPHY_MAC_SEL BIT(1)

/* Top misc registers */
Expand All @@ -716,7 +716,7 @@ Signed-off-by: Daniel Golle <[email protected]>
#define USB_PHY_SWITCH_REG 0x218
#define QPHY_SEL_MASK GENMASK(1, 0)
#define SGMII_QPHY_SEL 0x2
@@ -591,6 +613,8 @@
@@ -592,6 +614,8 @@
#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)

Expand All @@ -725,7 +725,7 @@ Signed-off-by: Daniel Golle <[email protected]>
#define MTK_FE_CDM1_FSM 0x220
#define MTK_FE_CDM2_FSM 0x224
#define MTK_FE_CDM3_FSM 0x238
@@ -599,6 +623,11 @@
@@ -600,6 +624,11 @@
#define MTK_FE_CDM6_FSM 0x328
#define MTK_FE_GDM1_FSM 0x228
#define MTK_FE_GDM2_FSM 0x22C
Expand All @@ -737,7 +737,7 @@ Signed-off-by: Daniel Golle <[email protected]>

#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))

@@ -723,12 +752,8 @@ enum mtk_clks_map {
@@ -724,12 +753,8 @@ enum mtk_clks_map {
MTK_CLK_ETHWARP_WOCPU2,
MTK_CLK_ETHWARP_WOCPU1,
MTK_CLK_ETHWARP_WOCPU0,
Expand All @@ -750,7 +750,7 @@ Signed-off-by: Daniel Golle <[email protected]>
MTK_CLK_TOP_ETH_GMII_SEL,
MTK_CLK_TOP_ETH_REFCK_50M_SEL,
MTK_CLK_TOP_ETH_SYS_200M_SEL,
@@ -799,19 +824,9 @@ enum mtk_clks_map {
@@ -800,19 +825,9 @@ enum mtk_clks_map {
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
BIT_ULL(MTK_CLK_CRYPTO) | \
Expand All @@ -770,7 +770,7 @@ Signed-off-by: Daniel Golle <[email protected]>
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
@@ -945,6 +960,8 @@ enum mkt_eth_capabilities {
@@ -946,6 +961,8 @@ enum mkt_eth_capabilities {
MTK_RGMII_BIT = 0,
MTK_TRGMII_BIT,
MTK_SGMII_BIT,
Expand All @@ -779,7 +779,7 @@ Signed-off-by: Daniel Golle <[email protected]>
MTK_ESW_BIT,
MTK_GEPHY_BIT,
MTK_MUX_BIT,
@@ -965,8 +982,11 @@ enum mkt_eth_capabilities {
@@ -966,8 +983,11 @@ enum mkt_eth_capabilities {
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
Expand All @@ -791,7 +791,7 @@ Signed-off-by: Daniel Golle <[email protected]>

/* PATH BITS */
MTK_ETH_PATH_GMAC1_RGMII_BIT,
@@ -974,14 +994,21 @@ enum mkt_eth_capabilities {
@@ -975,14 +995,21 @@ enum mkt_eth_capabilities {
MTK_ETH_PATH_GMAC1_SGMII_BIT,
MTK_ETH_PATH_GMAC2_RGMII_BIT,
MTK_ETH_PATH_GMAC2_SGMII_BIT,
Expand All @@ -813,7 +813,7 @@ Signed-off-by: Daniel Golle <[email protected]>
#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
@@ -1004,10 +1031,16 @@ enum mkt_eth_capabilities {
@@ -1005,10 +1032,16 @@ enum mkt_eth_capabilities {
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
Expand All @@ -830,7 +830,7 @@ Signed-off-by: Daniel Golle <[email protected]>

/* Supported path present on SoCs */
#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
@@ -1015,8 +1048,13 @@ enum mkt_eth_capabilities {
@@ -1016,8 +1049,13 @@ enum mkt_eth_capabilities {
#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
Expand All @@ -844,7 +844,7 @@ Signed-off-by: Daniel Golle <[email protected]>

#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
@@ -1024,7 +1062,12 @@ enum mkt_eth_capabilities {
@@ -1025,7 +1063,12 @@ enum mkt_eth_capabilities {
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
Expand All @@ -857,7 +857,7 @@ Signed-off-by: Daniel Golle <[email protected]>

/* MUXes present on SoCs */
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
@@ -1043,10 +1086,20 @@ enum mkt_eth_capabilities {
@@ -1044,10 +1087,20 @@ enum mkt_eth_capabilities {
(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
MTK_SHARED_SGMII)

Expand All @@ -878,7 +878,7 @@ Signed-off-by: Daniel Golle <[email protected]>
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))

#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
@@ -1078,8 +1131,12 @@ enum mkt_eth_capabilities {
@@ -1079,8 +1132,12 @@ enum mkt_eth_capabilities {
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_RSTCTRL_PPE1 | MTK_SRAM)

Expand All @@ -893,7 +893,7 @@ Signed-off-by: Daniel Golle <[email protected]>

struct mtk_tx_dma_desc_info {
dma_addr_t addr;
@@ -1324,6 +1381,9 @@ struct mtk_mac {
@@ -1325,6 +1382,9 @@ struct mtk_mac {
struct device_node *of_node;
struct phylink *phylink;
struct phylink_config phylink_config;
Expand All @@ -903,7 +903,7 @@ Signed-off-by: Daniel Golle <[email protected]>
struct mtk_eth *hw;
struct mtk_hw_stats *hw_stats;
__be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
@@ -1447,6 +1507,19 @@ static inline u32 mtk_get_ib2_multicast_
@@ -1448,6 +1508,19 @@ static inline u32 mtk_get_ib2_multicast_
return MTK_FOE_IB2_MULTICAST;
}

Expand All @@ -923,7 +923,7 @@ Signed-off-by: Daniel Golle <[email protected]>
/* read the hardware status register */
void mtk_stats_update_mac(struct mtk_mac *mac);

@@ -1455,8 +1528,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
@@ -1456,8 +1529,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);

int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
Expand Down

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