This was initially a group project for my second year Instruction Set Architectures module. I'm looking to redo it, modifying the components and layout to implement a very basic RISC-V processor, before moving onto adding more components.
Currently on hold while I'm learning about more advanced computer architectures, such as dynamic scheduling and speculation (everywhere...)
- Add an AES unit for encryption/decryption tasks in execute stage
- Implement an entirely separate Dynamically Scheduled Processor, based on Tomasulo