Merge branch 'master' into protocol-bug

.buildkite/pipeline.yml

@@ -36,41 +36,43 @@ steps:
     timeout_in_minutes: 60
     agents:
       fault2: "true"
-  - command: |
-      # set up environment
-      source /etc/environment
-      echo $$PATH
-
-      # create conda env
-      wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh
-      chmod +x Miniconda3-latest-Linux-x86_64.sh
-      ./Miniconda3-latest-Linux-x86_64.sh -b -u -p $$PWD/miniconda
-      export PATH=$$PWD/miniconda/bin:$$PATH
-      conda install python==3.8 -y -q
-
-      # install python dependencies for testing
-      pip install wheel
-      pip install "pytest<6"
-      pip install pytest-cov pytest-pycodestyle
-      pip install vcdvcd decorator kratos
-      pip install --upgrade "mantle>=2.0.0"
-      pip install DeCiDa scipy numpy
 
-      # use the latest cmake
-      pip install cmake
+#   - command: |
+#       # set up environment
+#       source /etc/environment
+#       echo $$PATH
+# 
+#       # create conda env
+#       wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh
+#       chmod +x Miniconda3-latest-Linux-x86_64.sh
+#       ./Miniconda3-latest-Linux-x86_64.sh -b -u -p $$PWD/miniconda
+#       export PATH=$$PWD/miniconda/bin:$$PATH
+#       conda install python==3.8 -y -q
+# 
+#       # install python dependencies for testing
+#       pip install wheel
+#       pip install "pytest<6"
+#       pip install pytest-cov pytest-pycodestyle
+#       pip install vcdvcd decorator kratos
+#       pip install --upgrade "mantle>=2.0.0"
+#       pip install DeCiDa scipy numpy
+# 
+#       # use the latest cmake
+#       pip install cmake
+# 
+#       # install fault
+#       pip install -e .
+#       
+#       # run tests
+#       pytest --pycodestyle --cov-report=xml --cov=fault tests/ -v -r s
+# 
+#       # upload coverage results
+#       bash <(curl -s https://codecov.io/bash)
+# 
+#       # deactivate virtual environment
+#       deactivate
+#     label: "fpga_verif"
+#     timeout_in_minutes: 60
+#     agents:
+#         fpga_verif: "true"
 
-      # install fault
-      pip install -e .
-      
-      # run tests
-      pytest --pycodestyle --cov-report=xml --cov=fault tests/ -v -r s
-
-      # upload coverage results
-      bash <(curl -s https://codecov.io/bash)
-
-      # deactivate virtual environment
-      deactivate
-    label: "fpga_verif"
-    timeout_in_minutes: 60
-    agents:
-        fpga_verif: "true"

.github/workflows/macos.yml

@@ -20,7 +20,7 @@ jobs:
       uses: conda-incubator/setup-miniconda@v2
       with:
         auto-update-conda: true
-        python-version: 3.7
+        python-version: 3.8
     - name: Install verilator
       shell: bash
       run: |

conftest.py

@@ -1,14 +1,11 @@
 import pytest
-from magma import clear_cachedFunctions
-import magma
 import logging
+from magma.util import reset_global_context
 
 collect_ignore = ["src"]  # pip folder that contains dependencies like magma
 
 
 @pytest.fixture(autouse=True)
 def magma_test():
-    clear_cachedFunctions()
-    magma.frontend.coreir_.ResetCoreIR()
-    magma.generator.reset_generator_cache()
+    reset_global_context()
     logging.getLogger().setLevel(logging.DEBUG)

fault/assert_immediate.py

@@ -1,13 +1,12 @@
 import magma as m
-from fault.property import Posedge
-from fault.assert_utils import add_compile_guards
+from fault.assert_utils import add_compile_guards, get_when_cond
 
 
 def _make_assert(type_, cond, success_msg=None, failure_msg=None,
-                 severity="error", name=None, compile_guard=None, delay=False,
-                 inline_wire_prefix=None):
-    if inline_wire_prefix is None:
-        inline_wire_prefix = "_FAULT_ASSERT_WIRE_"
+                 severity="error", name=None, compile_guard=None, delay=False):
+    if (when_cond := get_when_cond()) is not None:
+        cond = ~when_cond | cond
+
     success_msg_str = ""
     if success_msg is not None:
         success_msg_str = f" $display(\"{success_msg}\");"
@@ -37,9 +36,7 @@ def _make_assert(type_, cond, success_msg=None, failure_msg=None,
 end
 """
     assert_str = add_compile_guards(compile_guard, assert_str)
-    m.inline_verilog(
-        assert_str, inline_wire_prefix=inline_wire_prefix,
-        **format_args, type_=type_)
+    m.inline_verilog2(assert_str, **format_args, type_=type_)
 
 
 def _add_docstr(fn):
@@ -65,21 +62,20 @@ def _add_docstr(fn):
 
 @_add_docstr
 def assert_immediate(cond, success_msg=None, failure_msg=None, severity="error",
-                     name=None, compile_guard=None, inline_wire_prefix=None):
+                     name=None, compile_guard=None):
     _make_assert("always @(*)", cond, success_msg, failure_msg, severity, name,
-                 compile_guard, inline_wire_prefix=inline_wire_prefix)
+                 compile_guard)
 
 
 @_add_docstr
 def assert_final(cond, success_msg=None, failure_msg=None, severity="error",
-                 name=None, compile_guard=None, inline_wire_prefix=None):
+                 name=None, compile_guard=None):
     _make_assert("final", cond, success_msg, failure_msg, severity, name,
-                 compile_guard, inline_wire_prefix=inline_wire_prefix)
+                 compile_guard)
 
 
 @_add_docstr
 def assert_initial(cond, success_msg=None, failure_msg=None, severity="error",
-                   name=None, compile_guard=None, inline_wire_prefix=None):
+                   name=None, compile_guard=None):
     _make_assert("initial", cond, success_msg, failure_msg, severity, name,
-                 compile_guard, delay=True,
-                 inline_wire_prefix=inline_wire_prefix)
+                 compile_guard, delay=True)

fault/assert_utils.py

@@ -1,3 +1,7 @@
+from magma.bit import Bit
+from magma.when import get_curr_block as get_curr_when_block, no_when
+
+
 def add_compile_guards(compile_guard, verilog_str):
     if compile_guard is None:
         return verilog_str
@@ -14,3 +18,16 @@ def add_compile_guards(compile_guard, verilog_str):
 `endif
 """
     return verilog_str
+
+
+def get_when_cond():
+    """If active when cond, return a boolean that is true when the when
+    condition is true.
+    """
+    if not get_curr_when_block():
+        return None
+    with no_when():
+        when_cond = Bit()
+        when_cond @= 0
+    when_cond @= 1
+    return when_cond

fault/property.py

@@ -3,7 +3,7 @@
 from fault.sva import SVAProperty
 from fault.expression import Expression, UnaryOp, BinaryOp
 from fault.infix import Infix
-from fault.assert_utils import add_compile_guards
+from fault.assert_utils import add_compile_guards, get_when_cond
 
 
 class Property:
@@ -155,7 +155,7 @@ def _codegen_slice(self, value):
 
     def _compile(self, value):
         if isinstance(value, PropertyUnaryOp):
-            return f"{value.op_str} {self._compile(value.arg)}"
+            return f"({value.op_str} ({self._compile(value.arg)}))"
         # TODO: Refactor getitem properties to share code
         if isinstance(value, Delay):
             result = ""
@@ -221,6 +221,8 @@ def _compile(self, value):
             # Double escape on curly braces since this will run through format
             # inside inline_verilog logic
             return f"{{{{{contents}}}}}"
+        if isinstance(value, bool):
+            return f"1'b{int(value)}"
         if isinstance(value, int):
             return str(value)
         if isinstance(value, BinaryOp):
@@ -245,8 +247,10 @@ def compile(self, prop):
         return compiled
 
 
-def _make_statement(statement, prop, on, disable_iff, compile_guard, name,
-                    inline_wire_prefix):
+def _make_statement(statement, prop, on, disable_iff, compile_guard, name):
+    if (when_cond := get_when_cond()) is not None:
+        prop = when_cond | implies | prop
+
     format_args = {}
     _compiler = _Compiler(format_args)
     prop = _compiler.compile(prop)
@@ -260,26 +264,19 @@ def _make_statement(statement, prop, on, disable_iff, compile_guard, name,
             raise TypeError("Expected string for name")
         prop_str = f"{name}: {prop_str}"
     prop_str = add_compile_guards(compile_guard, prop_str)
-    m.inline_verilog(prop_str, inline_wire_prefix=inline_wire_prefix,
-                     **format_args)
+    m.inline_verilog2(prop_str, **format_args)
 
 
-def assert_(prop, on, disable_iff=None, compile_guard=None, name=None,
-            inline_wire_prefix="_FAULT_ASSERT_WIRE_"):
-    _make_statement("assert", prop, on, disable_iff, compile_guard, name,
-                    inline_wire_prefix)
+def assert_(prop, on, disable_iff=None, compile_guard=None, name=None):
+    _make_statement("assert", prop, on, disable_iff, compile_guard, name)
 
 
-def cover(prop, on, disable_iff=None, compile_guard=None, name=None,
-          inline_wire_prefix="_FAULT_COVER_WIRE_"):
-    _make_statement("cover", prop, on, disable_iff, compile_guard, name,
-                    inline_wire_prefix)
+def cover(prop, on, disable_iff=None, compile_guard=None, name=None):
+    _make_statement("cover", prop, on, disable_iff, compile_guard, name)
 
 
-def assume(prop, on, disable_iff=None, compile_guard=None, name=None,
-           inline_wire_prefix="_FAULT_ASSUME_WIRE_"):
-    _make_statement("assume", prop, on, disable_iff, compile_guard, name,
-                    inline_wire_prefix)
+def assume(prop, on, disable_iff=None, compile_guard=None, name=None):
+    _make_statement("assume", prop, on, disable_iff, compile_guard, name)
 
 
 class Sequence:
@@ -328,6 +325,11 @@ class Not(PropertyUnaryOp):
     def __init__(self, arg):
         self.arg = arg
 
+    def __or__(self, other):
+        if isinstance(other, Property):
+            return other.__ror__(self)
+        return super().__or__(other)
+
 
 def not_(arg):
     return Not(arg)

fault/tester/base.py

@@ -1,5 +1,6 @@
 import logging
 import magma as m
+from magma.clock import is_clock_or_nested_clock
 from abc import abstractmethod
 from ..wrapper import CircuitWrapper, PortWrapper
 from ..select_path import SelectPath
@@ -57,7 +58,7 @@ def _find_default_clock(self, ports):
             next_clock = None
             if isinstance(port, m.Clock):
                 next_clock = port
-            elif isinstance(port, (m.Array, m.Tuple)):
+            elif is_clock_or_nested_clock(type(port), (m.Clock,)):
                 nested_clock = self._find_default_clock(port.ts)
                 if nested_clock is not None:
                     next_clock = nested_clock

setup.py

@@ -13,7 +13,7 @@
 
 setup(
     name='fault',
-    version='3.1.3',
+    version='3.4.0',
     description=DESCRIPTION,
     scripts=[],
     packages=[
@@ -22,8 +22,6 @@
     ],
     install_requires=[
         "astor",
-        "coreir",
-        "cosa",
         "z3-solver",
         "hwtypes",
         "magma-lang>=2.2.3",