Fix style

leonardt · Nov 18, 2023 · 1cc700f · 1cc700f
1 parent d730f71
commit 1cc700f
Showing 1 changed file with 12 additions and 7 deletions.
diff --git a/tests/test_property.py b/tests/test_property.py
@@ -299,8 +299,10 @@ def test_eventually(sva, capsys):
     class Main(m.Circuit):
         io = m.IO(write=m.In(m.Bit), read=m.In(m.Bit)) + m.ClockIO()
         if sva:
-            f.assert_(f.sva(io.write == 1, f"|-> s_eventually", io.read == 1),
-                      on=f.posedge(io.CLK))
+            f.assert_(
+                f.sva(io.write == 1, "|-> s_eventually", io.read == 1),
+                on=f.posedge(io.CLK)
+            )
         else:
             f.assert_((io.write == 1) | f.implies | f.eventually |
                       (io.read == 1), on=f.posedge(io.CLK))
@@ -819,11 +821,14 @@ class Foo(m.Circuit):
         io.ready @= 1
         if use_sva:
             f.assert_(
-                f.sva(f.sequence(f.not_(~(io.valid & io.ready.value() & io.eop))),
-                      "throughout",
-                      # Note: need sequences to wrap parens
-                      f.sequence(f.sva((io.valid & io.ready.value() & io.sop),
-                                       "[-> 2]"))),
+                f.sva(
+                    f.sequence(
+                        f.not_(~(io.valid & io.ready.value() & io.eop))
+                    ),
+                    "throughout",
+                    # Note: need sequences to wrap parens
+                    f.sequence(f.sva((io.valid & io.ready.value() & io.sop),
+                                     "[-> 2]"))),
                 name="eop_must_happen_btn_two_sop_A",
                 on=f.posedge(io.CLK),
                 disable_iff=f.not_(io.RESETN)