Try setting magma opts

leonardt · Nov 22, 2023 · 417d213 · 417d213
1 parent 2c41d09
commit 417d213
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/tests/test_property.py b/tests/test_property.py
@@ -917,6 +917,8 @@ class Main(m.Circuit):
     tester.compile_and_run("system-verilog", simulator="ncsim",
                            magma_output="mlir-verilog", flags=["-sv"],
                            skip_compile=True, disp_type="realtime",
+                           magma_opts={"sv": True,
+                                       "disable_initial_blocks": True},
                            coverage=True)
 
     out, _ = capsys.readouterr()
@@ -933,6 +935,8 @@ class Main(m.Circuit):
     tester.advance_cycle()
     tester.compile_and_run("system-verilog", simulator="ncsim",
                            flags=["-sv"], skip_compile=True,
+                           magma_opts={"sv": True,
+                                       "disable_initial_blocks": True},
                            disp_type="realtime", coverage=True)
 
     out, _ = capsys.readouterr()
@@ -953,6 +957,8 @@ class Main(m.Circuit):
                            flags=["-sv"],
                            skip_compile=True,
                            disp_type="realtime",
+                           magma_opts={"sv": True,
+                                       "disable_initial_blocks": True},
                            coverage=True)
 
     out, _ = capsys.readouterr()