Disable initial blocks

leonardt · Nov 21, 2023 · c3bc2cb · c3bc2cb
1 parent 49904c3
commit c3bc2cb
Showing 1 changed file with 14 additions and 6 deletions.
diff --git a/tests/test_property.py b/tests/test_property.py
@@ -893,9 +893,13 @@ class Main(m.Circuit):
     tester.advance_cycle()
     tester.circuit.I = 1
     tester.advance_cycle()
-    tester.compile_and_run("system-verilog", simulator="ncsim",
-                           magma_output="mlir-verilog", flags=["-sv"],
-                           magma_opts={"sv": True}, disp_type="realtime",
+    tester.compile_and_run("system-verilog",
+                           simulator="ncsim",
+                           magma_output="mlir-verilog",
+                           flags=["-sv"],
+                           magma_opts={"sv": True,
+                                       "disable_initial_blocks": True},
+                           disp_type="realtime",
                            coverage=True)
 
     out, _ = capsys.readouterr()
@@ -941,9 +945,13 @@ class Main(m.Circuit):
     tester.circuit.I = 1
     tester.advance_cycle()
     tester.circuit.I = 0
-    tester.compile_and_run("system-verilog", simulator="ncsim",
-                           magma_output="mlir-verilog", flags=["-sv"],
-                           magma_opts={"sv": True}, disp_type="realtime",
+    tester.compile_and_run("system-verilog",
+                           simulator="ncsim",
+                           magma_output="mlir-verilog",
+                           flags=["-sv"],
+                           magma_opts={"sv": True,
+                                       "disable_initial_blocks": True},
+                           disp_type="realtime",
                            coverage=True)
 
     out, _ = capsys.readouterr()