Fix sequence

leonardt · Nov 28, 2023 · e88d916 · e88d916
1 parent c5e7649
commit e88d916
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/tests/test_property.py b/tests/test_property.py
@@ -953,10 +953,10 @@ class Main(m.Circuit):
     tester.clear()
     tester.circuit.CLK = 0
     tester.circuit.S = 1
-    tester.circuit.I = 0
-    tester.advance_cycle()
     tester.circuit.I = 1
     tester.advance_cycle()
+    tester.circuit.I = 0
+    tester.advance_cycle()
     tester.compile_and_run("system-verilog",
                            simulator="ncsim",
                            magma_output="mlir-verilog",