Merge branch 'fix-deprecation' into when-cover

tests/test_assert_immediate.py

@@ -58,10 +58,11 @@ class Foo(m.Circuit):
             "error": "%Error:",
         }[severity]
         msg += " Foo.v:9: "
-        # TODO: verilator 5.016 needs this
-        # if severity == "error":
-        #     msg += "Assertion failed in "
-        msg += "Assertion failed in "
+        if verilator_version() >= 5.016:
+            if severity == "error":
+                msg += "Assertion failed in "
+        else:
+            msg += "Assertion failed in "
         msg += "TOP.Foo"
         if name is not None:
             msg += f".{name}"

tests/test_magma_opts.py

@@ -1,3 +1,4 @@
+import tempfile
 import magma as m
 import fault as f
 
@@ -12,4 +13,7 @@ class Foo(m.Circuit):
     tester.eval()
     tester.circuit.O.expect(4)
 
-    tester.compile_and_run("verilator", magma_opts={"verilog_prefix": "bar_"})
+    with tempfile.TemporaryDirectory(dir=".") as tempdir:
+        tester.compile_and_run("verilator",
+                               magma_opts={"verilog_prefix": "bar_"},
+                               directory=tempdir)

tests/test_magma_protocol.py

@@ -1,3 +1,4 @@
+import tempfile
 from typing import Optional
 import magma as m
 import fault
@@ -45,4 +46,6 @@ class Bar(m.Circuit):
     tester.circuit.O.expect(BitVector[8](0xDE << 2) |
                             (BitVector[8](0xDE) << 1)[0] |
                             BitVector[8](0xDE)[0])
-    tester.compile_and_run("verilator")
+
+    with tempfile.TemporaryDirectory(dir=".") as _dir:
+        tester.compile_and_run("verilator", directory=_dir)

tests/test_no_coreir.py

@@ -1,9 +1,9 @@
+import tempfile
+
 import hwtypes as ht
 import fault as f
 import magma as m
 
-import pytest
-
 
 def test_fault_no_coreir():
     class Foo(m.Circuit):
@@ -15,4 +15,6 @@ class Foo(m.Circuit):
     tester.eval()
     tester.circuit.O.expect(I & 0xFF)
 
-    tester.compile_and_run("verilator", magma_output="mlir-verilog")
+    with tempfile.TemporaryDirectory(dir=".") as tempdir:
+        tester.compile_and_run("verilator", magma_output="mlir-verilog",
+                               directory=tempdir)

tests/test_protocol.py

@@ -1,3 +1,4 @@
+import tempfile
 
 import magma as m
 import fault
@@ -48,4 +49,6 @@ def test_proto():
     tester.circuit.val = 1
     tester.eval()
     tester.circuit.O.expect(2)
-    tester.compile_and_run("verilator", flags=['-Wno-unused'])
+    with tempfile.TemporaryDirectory(dir=".") as tempdir:
+        tester.compile_and_run("verilator", flags=['-Wno-unused'],
+                               directory=tempdir)

tests/test_pysv.py

@@ -24,7 +24,7 @@ def run_tester(tester, target, simulator):
         # "disp_type": "realtime",
         "simulator": simulator,
         "magma_opts": {"sv": True},
-        "tmp_dir": False
+        "tmp_dir": True
     }
 
     if target == "verilator":

tests/test_ready_valid.py

@@ -27,6 +27,7 @@ def test_basic_ready_valid_sequence():
         {"I": I, "O": O},
         "verilator",
         compile_and_run_kwargs={'magma_output': 'mlir-verilog',
+                                'tmp_dir': True,
                                 'magma_opts': {'flatten_all_tuples': True}}
     )
 
@@ -42,6 +43,7 @@ def test_basic_ready_valid_sequence_fail():
             {"I": I, "O": O},
             "verilator",
             compile_and_run_kwargs={'magma_output': 'mlir-verilog',
+                                    'tmp_dir': True,
                                     'magma_opts': {'flatten_all_tuples': True}}
         )
 
@@ -71,7 +73,8 @@ def test_lifted_ready_valid_sequence_simple():
     tester.compile_and_run("verilator", disp_type="realtime",
                            flags=['-Wno-UNUSED'],
                            magma_output="mlir-verilog",
-                           magma_opts={"flatten_all_tuples": True})
+                           magma_opts={"flatten_all_tuples": True},
+                           tmp_dir=True)
 
 
 def test_lifted_ready_valid_sequence_simple_fail():
@@ -90,7 +93,8 @@ def test_lifted_ready_valid_sequence_simple_fail():
     with pytest.raises(AssertionError):
         tester.compile_and_run("verilator", disp_type="realtime",
                                magma_output="mlir-verilog",
-                               magma_opts={"flatten_all_tuples": True})
+                               magma_opts={"flatten_all_tuples": True},
+                               tmp_dir=True)
 
 
 def test_lifted_ready_valid_sequence_changing_inc():
@@ -110,4 +114,5 @@ def test_lifted_ready_valid_sequence_changing_inc():
     tester.compile_and_run("verilator", disp_type="realtime",
                            flags=['-Wno-UNUSED'],
                            magma_output="mlir-verilog",
-                           magma_opts={"flatten_all_tuples": True})
+                           magma_opts={"flatten_all_tuples": True},
+                           tmp_dir=True)

tests/test_tester/test_call.py

@@ -59,7 +59,6 @@ def test_call_interface_clock(target, simulator, caplog):
         tester.step(2)
         tester(3, 2).expect(ops[i](BitVector[16](3), BitVector[16](2)))
     with tempfile.TemporaryDirectory(dir=".") as _dir:
-        _dir = "build"
         if target == "verilator":
             tester.compile_and_run(target, directory=_dir,
                                    flags=["-Wno-unused"])

tests/test_tester/test_sequence_tester.py

@@ -1,3 +1,4 @@
+import tempfile
 import pytest
 
 import magma as m
@@ -76,4 +77,6 @@ def test_simple_alu_sequence(circuit, driver, monitor, clock):
 
     tester = SequenceTester(circuit, driver, monitor, sequence, clock=clock)
 
-    tester.compile_and_run("verilator", flags=['-Wno-UNUSED'])
+    with tempfile.TemporaryDirectory(dir=".") as tempdir:
+        tester.compile_and_run("verilator", flags=['-Wno-UNUSED'],
+                               directory=tempdir)

tests/test_tester/test_synchronous.py

@@ -1,4 +1,6 @@
+import tempfile
 import pytest
+
 from fault import SynchronousTester
 import magma as m
 from hwtypes import BitVector
@@ -30,7 +32,8 @@ def test_synchronous_basic(target, simulator):
         tester.advance_cycle()
 
     if target == "verilator":
-        tester.compile_and_run("verilator")
+        with tempfile.TemporaryDirectory(dir=".") as tempdir:
+            tester.compile_and_run("verilator", directory=tempdir)
     else:
         tester.compile_and_run(target, simulator=simulator,
                                magma_opts={"sv": True})