[magma v3.0.0] Upgrade to magma v3.0.0

.buildkite/pipeline.yml

@@ -15,7 +15,7 @@ steps:
       pip install "pytest<6"
       pip install coverage pytest-pycodestyle
       pip install --upgrade "mantle>=2.0.0"
-      pip install vcdvcd decorator kratos
+      pip install vcdvcd decorator kratos importlib_resources
       pip install DeCiDa scipy numpy
 
       # install fault

.github/workflows/deploy.yml

@@ -30,6 +30,7 @@ jobs:
     - name: Install Python packages
       shell: bash -l {0}
       run: |
+          pip install importlib_resources
           pip install "pytest<6"
           pip install pytest-cov pytest-pycodestyle
           pip install mantle>=2.0.0  # for tests.common

.github/workflows/linux.yml

@@ -21,6 +21,7 @@ jobs:
     - name: Install Python packages
       shell: bash -l {0}
       run: |
+          pip install importlib_resources
           pip install "pytest<6"
           pip install pytest-cov pytest-pycodestyle
           pip install mantle>=2.0.0  # for tests.common

.github/workflows/macos.yml

@@ -31,6 +31,7 @@ jobs:
     - name: Install Python packages
       shell: bash -l {0}
       run: |
+          pip install importlib_resources
           pip install "pytest<6"
           pip install pytest-cov pytest-pycodestyle
           pip install mantle>=2.0.0  # for tests.common

README.md

@@ -45,14 +45,13 @@ Check out the [fault tutorial](https://github.com/leonardt/fault/tree/master/tut
 Here is a simple ALU defined in magma.
 ```python
 import magma as m
-import mantle
 
 
 class ConfigReg(m.Circuit):
     io = m.IO(D=m.In(m.Bits[2]), Q=m.Out(m.Bits[2])) + \
         m.ClockIO(has_ce=True)
 
-    reg = mantle.Register(2, has_ce=True, name="conf_reg")
+    reg = m.Register(m.Bits[2], has_enable=True)(name="conf_reg")
     io.Q @= reg(io.D, CE=io.CE)
 
 
@@ -66,7 +65,7 @@ class SimpleALU(m.Circuit):
     ) + m.ClockIO()
 
     opcode = ConfigReg(name="config_reg")(io.config_data, CE=io.config_en)
-    io.c @= mantle.mux(
+    io.c @= m.mux(
         [io.a + io.b, io.a - io.b, io.a * io.b, io.a ^ io.b], opcode)
 ```
 

examples/sv_tb/sv_tb.py

@@ -1,24 +1,26 @@
 import random
 
 import magma as m
-import mantle
 import fault
 
 
-class Queue(m.Generator2):
-    def __init__(self, T, entries, with_bug=False):
-        assert entries >= 0
+class Queue(m.Generator):
+    def __init__(self, T, num_bits, with_bug=False):
+        assert num_bits >= 0
         self.io = m.IO(
             # Flipped since enq/deq is from perspective of the client
             enq=m.DeqIO[T],
             deq=m.EnqIO[T]
         ) + m.ClockIO()
 
-        ram = m.Memory(entries, T)()
-        enq_ptr = mantle.CounterModM(entries, entries.bit_length(),
-                                     has_ce=True, cout=False)
-        deq_ptr = mantle.CounterModM(entries, entries.bit_length(),
-                                     has_ce=True, cout=False)
+        ram = m.Memory(2 ** num_bits, T)()
+        _Pointer = m.mantle.Counter(
+            (2 ** (num_bits + 1)),
+            has_enable=True,
+            has_cout=False
+        )
+        enq_ptr = _Pointer()
+        deq_ptr = _Pointer()
         maybe_full = m.Register(init=False, has_enable=True)()
 
         ptr_match = enq_ptr.O == deq_ptr.O
@@ -50,7 +52,7 @@ def ispow2(n):
 
 def test_queue(with_bug):
     T = m.Bits[8]
-    Queue4x8 = Queue(T, 4, with_bug=with_bug)
+    Queue4x8 = Queue(T, 2, with_bug=with_bug)
 
     class Monitor(m.Circuit):
         io = m.IO(
@@ -111,8 +113,11 @@ class DUT(m.Circuit):
         tester.circuit.deq.ready = random.randint(0, 1)
         tester.advance_cycle()
     try:
-        tester.compile_and_run("verilator", flags=["--assert"],
-                               magma_opts={"inline": True})
+        tester.compile_and_run(
+            "verilator",
+            flags=["--assert"],
+            magma_output="mlir-verilog"
+        )
         assert not with_bug
     except AssertionError:
         assert with_bug

examples/test_simple_alu.py

@@ -1,5 +1,4 @@
 import magma as m
-import mantle
 import operator
 import fault
 import pytest
@@ -11,7 +10,7 @@ class ConfigReg(m.Circuit):
     io = m.IO(D=m.In(m.Bits[2]), Q=m.Out(m.Bits[2])) + \
         m.ClockIO(has_ce=True)
 
-    reg = mantle.Register(2, has_ce=True, name="conf_reg")
+    reg = m.Register(m.Bits[2], has_enable=True)(name="conf_reg")
     io.Q @= reg(io.D, CE=io.CE)
 
 
@@ -24,7 +23,7 @@ class SimpleALU(m.Circuit):
               ) + m.ClockIO()
 
     opcode = ConfigReg(name="config_reg")(io.config_data, CE=io.config_en)
-    io.c @= mantle.mux(
+    io.c @= m.mux(
         [io.a + io.b, io.a - io.b, io.a * io.b, io.a ^ io.b], opcode)
 
 

fault/assert_immediate.py

@@ -36,7 +36,7 @@ def _make_assert(type_, cond, success_msg=None, failure_msg=None,
 end
 """
     assert_str = add_compile_guards(compile_guard, assert_str)
-    m.inline_verilog2(assert_str, **format_args, type_=type_)
+    m.inline_verilog(assert_str, **format_args, type_=type_)
 
 
 def _add_docstr(fn):

fault/property.py

@@ -264,7 +264,7 @@ def _make_statement(statement, prop, on, disable_iff, compile_guard, name):
             raise TypeError("Expected string for name")
         prop_str = f"{name}: {prop_str}"
     prop_str = add_compile_guards(compile_guard, prop_str)
-    m.inline_verilog2(prop_str, **format_args)
+    m.inline_verilog(prop_str, **format_args)
 
 
 def assert_(prop, on, disable_iff=None, compile_guard=None, name=None):

setup.py

@@ -24,7 +24,7 @@
         "astor",
         "z3-solver",
         "hwtypes",
-        "magma-lang>=2.2.3",
+        "magma-lang>=3.0.0",
         "pyyaml",
         "scipy",
         "numpy",

tests/common.py

@@ -1,6 +1,5 @@
 import shutil
 import magma as m
-import mantle
 
 
 def pytest_sim_params(metafunc, *args, exclude=None):
@@ -93,9 +92,9 @@ class TestPeekCircuit(m.Circuit):
 
 class ConfigReg(m.Circuit):
     io = m.IO(D=m.In(m.Bits[2]), Q=m.Out(m.Bits[2])) + \
-        m.ClockIO(has_ce=True)
+        m.ClockIO(has_enable=True)
 
-    reg = mantle.Register(2, has_ce=True, name="conf_reg")
+    reg = m.Register(m.Bits[2], has_enable=True)(name="conf_reg")
     io.Q @= reg(io.D, CE=io.CE)
 
 
@@ -108,7 +107,7 @@ class SimpleALU(m.Circuit):
               ) + m.ClockIO()
 
     opcode = ConfigReg(name="config_reg")(io.config_data, CE=io.config_en)
-    io.c @= mantle.mux(
+    io.c @= m.mux(
         # udiv not implemented
         # [io.a + io.b, io.a - io.b, io.a * io.b, io.a / io.b], opcode)
         # use arbitrary fourth op

tests/test_env_mod.py

@@ -1,5 +1,4 @@
 import fault
-import mantle
 import magma as m
 from .common import pytest_sim_params
 

tests/test_expressions.py

@@ -8,7 +8,6 @@
 
 import fault
 import magma as m
-import mantle
 import hwtypes
 
 

tests/test_functional_tester.py

@@ -2,7 +2,6 @@
 from hwtypes import BitVector
 from fault.functional_tester import FunctionalTester
 import magma as m
-import mantle
 import tempfile
 import pytest
 
@@ -24,7 +23,7 @@ class Configurable(m.Circuit):
                   config_en=m.In(m.Enable), O=m.Out(m.Bits[32])
                   ) + m.ClockIO()
 
-        reg = mantle.Register(32, has_ce=True)
+        reg = m.Register(m.Bits[32], has_enable=True)()
 
         reg(io.config_data,
             CE=(io.config_addr == m.bits(1, 32)) & m.bit(io.config_en))

tests/test_power_domains.py

@@ -1,5 +1,4 @@
 import magma as m
-import mantle
 import fault
 from hwtypes import BitVector
 import pytest