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targets/siglent_sds1104xe: Review.
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enjoy-digital committed Oct 23, 2023
1 parent 71d8b17 commit 0d560bc
Showing 1 changed file with 2 additions and 1 deletion.
3 changes: 2 additions & 1 deletion litex_boards/targets/siglent_sds1104xe.py
Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,7 @@ def __init__(self, sys_clk_freq=100e6,
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))

# Etherbone.
self.add_etherbone(
phy = self.ethphy,
ip_address = "192.168.1.51",
Expand All @@ -112,7 +113,7 @@ def __init__(self, sys_clk_freq=100e6,
interface = "hybrid",
endianness = self.cpu.endianness)

## Software Interface.
# Software Interface.
ethmac = self.get_module("ethcore_etherbone").mac
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
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