tidy QMTech 7series boards, add missing bistream compression

litex-hub · Oct 24, 2023 · 57a345c · 57a345c
1 parent b1c00d2
commit 57a345c
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Showing 5 changed files with 20 additions and 9 deletions.
diff --git a/litex_boards/platforms/qmtech_artix7_fbg484.py b/litex_boards/platforms/qmtech_artix7_fbg484.py
@@ -161,16 +161,17 @@ def __init__(self, kgates=200, toolchain="vivado", with_daughterboard=False):
             connectors += daughterboard.connectors
 
         Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
+
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
-             "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"]
+            "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"]
         self.toolchain.additional_commands = \
             ["write_cfgmem -force -format bin -interface spix4 -size 16 "
-             "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+            "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 16]")
         self.add_platform_command("set_property CFGBVS VCCO [current_design]")
         self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
-        self.toolchain.f4pga_device = device
 
     def create_programmer(self):
         bscan_spi = f"bscan_spi_xc7a{self.kgates}t.bit"

diff --git a/litex_boards/platforms/qmtech_artix7_fgg676.py b/litex_boards/platforms/qmtech_artix7_fgg676.py
@@ -161,16 +161,17 @@ def __init__(self, kgates=100, toolchain="vivado", with_daughterboard=False):
             connectors += daughterboard.connectors
 
         Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
+
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
-             "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"]
+            "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"]
         self.toolchain.additional_commands = \
             ["write_cfgmem -force -format bin -interface spix4 -size 16 "
-             "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+            "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 16]")
         self.add_platform_command("set_property CFGBVS VCCO [current_design]")
         self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
-        self.toolchain.f4pga_device = device
 
     def create_programmer(self):
         bscan_spi = f"bscan_spi_xc7a{self.kgates}t.bit"

diff --git a/litex_boards/platforms/qmtech_wukong.py b/litex_boards/platforms/qmtech_wukong.py
@@ -207,11 +207,13 @@ def __init__(self, board_version=1, speed_grade=-2, toolchain="vivado"):
         else:
             io.extend(_io_v2)
         Xilinx7SeriesPlatform.__init__(self, "xc7a100t{}fgg676".format(speed_grade), io, _connectors,  toolchain=toolchain)
+
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
         self.toolchain.additional_commands = \
             ["write_cfgmem -force -format bin -interface spix4 -size 16 "
-             "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+            "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+
         self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 16]")
         if board_version < 2:
             self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk50_IBUF]")

diff --git a/litex_boards/platforms/qmtech_xc7a35t.py b/litex_boards/platforms/qmtech_xc7a35t.py
@@ -159,15 +159,16 @@ def __init__(self, toolchain="vivado", with_daughterboard=False):
             io += self.core_resources
 
         Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
+
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
         self.toolchain.additional_commands = \
             ["write_cfgmem -force -format bin -interface spix4 -size 16 "
-             "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+            "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+
         self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 15]")
         self.add_platform_command("set_property CFGBVS VCCO [current_design]")
         self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
-        self.toolchain.f4pga_device = device
 
     def create_programmer(self):
         bscan_spi = "bscan_spi_xc7a35t.bit"

diff --git a/litex_boards/platforms/qmtech_xc7k325t.py b/litex_boards/platforms/qmtech_xc7k325t.py
@@ -165,6 +165,12 @@ def __init__(self, toolchain="vivado", with_daughterboard=False):
 
         XilinxPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
 
+        self.toolchain.bitstream_commands = \
+            ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
+        self.toolchain.additional_commands = \
+            ["write_cfgmem -force -format bin -interface spix4 -size 16 "
+            "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
+
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
         self.add_platform_command("set_property INTERNAL_VREF 0.90  [get_iobanks 33]")