xu8_pe3: Fix clk_p/n on pcie_x8.

litex-hub · Jul 13, 2023 · 72a9510 · 72a9510
1 parent 18a3909
commit 72a9510
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/litex_boards/platforms/enclustra_mercury_xu8_pe3.py b/litex_boards/platforms/enclustra_mercury_xu8_pe3.py
@@ -54,8 +54,8 @@
 
     ("pcie_x8", 0, # GTH Bank 227 and 226.
         Subsignal("rst_n", Pins("AF2"), IOStandard("LVCMOS12"), Misc("PULLUP=TRUE")),
-        Subsignal("clk_p", Pins("H10")),
-        Subsignal("clk_n", Pins("H9")),
+        Subsignal("clk_p", Pins("B10")),
+        Subsignal("clk_n", Pins("B9")),
         Subsignal("rx_p",  Pins("D2 C4 B2 A4 H2 G4 F2 E4")),
         Subsignal("rx_n",  Pins("D1 C3 B1 A3 H1 G3 F1 E3")),
         Subsignal("tx_p",  Pins("D6 C8 B6 A8 H6 G8 F6 E8")),