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target/analog_pocket: Remove debug (Will be investigated externally).
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enjoy-digital committed Oct 27, 2023
1 parent 554cdaa commit 8792dd8
Showing 1 changed file with 0 additions and 54 deletions.
54 changes: 0 additions & 54 deletions litex_boards/targets/analog_pocket.py
Original file line number Diff line number Diff line change
Expand Up @@ -137,60 +137,6 @@ def __init__(self, pads, clock_domain="sys"):
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="video")


if False:
#./analog_pocket.py --uart-name="crossover" --with-video-framebuffer --csr-csv=csr.csv --build --load
# litex_server --jtag --jtag-config=openocd_usb_blaster.cfg
# litex_term crossover
# litescope_cli -r main_vfb_dma_source_source_last

# Add UART auto-flush.
self.uart.add_auto_tx_flush(sys_clk_freq=sys_clk_freq, timeout=1, interval=128)

# DMA/VTG Synchro Debug.
from litescope import LiteScopeAnalyzer
analyzer_signals = [
self.video_framebuffer.dma.source.valid,
self.video_framebuffer.dma.source.ready,
self.video_framebuffer.dma.source.last,
self.video_framebuffer.source.valid,
self.video_framebuffer.source.ready,
self.video_framebuffer.source.last,
self.video_framebuffer.vtg_sink.valid,
self.video_framebuffer.vtg_sink.ready,
self.video_framebuffer.vtg_sink.last,
]
self.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "sys",
samplerate = sys_clk_freq,
csr_csv = "analyzer.csv"
)


#!/usr/bin/env python3

# import time
#
# from litex import RemoteClient
#
# bus = RemoteClient()
# bus.open()
#
# # # #
#
# for i in range(640*10):
# bus.write(0x40c00000 + 4*i, 0x00000000)
# time.sleep(0.01)
#
# for i in range(640*10):
# bus.write(0x40c00000 + 4*i, 0xffffffff)
# time.sleep(0.1)

# # # #

# bus.close()

# Build --------------------------------------------------------------------------------------------

def main():
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