aliexpress_xc7k70t: Review/Cleanup.

- Cosmetic cleanups in platform. - Add clk50 constraint. - Remove JTAGBone specific support since now directly handled by LiteX.
litex-hub · Nov 9, 2023 · 8e3dc21 · 8e3dc21
1 parent 8f43cfe
commit 8e3dc21
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Showing 3 changed files with 47 additions and 51 deletions.
diff --git a/README.md b/README.md
@@ -97,6 +97,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
     ├── alchitry_cu
     ├── alchitry_mojo
     ├── aliexpress_xc7k420t
+    ├── aliexpress_xc7k70t
     ├── alinx_ax7010
     ├── alinx_axu2cga
     ├── analog_pocket

diff --git a/litex_boards/platforms/aliexpress_xc7k70t.py b/litex_boards/platforms/aliexpress_xc7k70t.py
@@ -42,15 +42,15 @@
     # SDRAM
     ("sdram_clock", 0, Pins("P23"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
     ("sdram", 0,
-        Subsignal("a", Pins("L25 L24 K23 M26 G25 F24 H26 F23 E23 J26 M25 G24")),
-        Subsignal("dq", Pins("T23 T25 T24 R25 R23 R26 P24 P25 F25 H24 E26 H23 E25 J24 D26 J23")),
-        Subsignal("ba", Pins("K25 M24")),
-        Subsignal("dm", Pins("N23 G26")),
+        Subsignal("a",     Pins("L25 L24 K23 M26 G25 F24 H26 F23 E23 J26 M25 G24")),
+        Subsignal("dq",    Pins("T23 T25 T24 R25 R23 R26 P24 P25 F25 H24 E26 H23 E25 J24 D26 J23")),
+        Subsignal("ba",    Pins("K25 M24")),
+        Subsignal("dm",    Pins("N23 G26")),
         Subsignal("ras_n", Pins("N24")),
         Subsignal("cas_n", Pins("K26")),
-        Subsignal("we_n", Pins("P26")),
-        Subsignal("cs_n", Pins("N26")),
-        Subsignal("cke", Pins("J25")),
+        Subsignal("we_n",  Pins("P26")),
+        Subsignal("cs_n",  Pins("N26")),
+        Subsignal("cke",   Pins("J25")),
         IOStandard("LVCMOS33"),
         Misc("SLEW = FAST")
     ),
@@ -103,14 +103,15 @@
 
     # HDMI out
     ("hdmi_out", 0,
-        Subsignal("clk_p",   Pins("E10"), IOStandard("TMDS_33")),
-        Subsignal("clk_n",   Pins("D10"), IOStandard("TMDS_33")),
-        Subsignal("data0_p", Pins("D9"),  IOStandard("TMDS_33")),
-        Subsignal("data0_n", Pins("D8"),  IOStandard("TMDS_33")),
-        Subsignal("data1_p", Pins("C9"),  IOStandard("TMDS_33")),
-        Subsignal("data1_n", Pins("B9"),  IOStandard("TMDS_33")),
-        Subsignal("data2_p", Pins("A9"),  IOStandard("TMDS_33")),
-        Subsignal("data2_n", Pins("A8"),  IOStandard("TMDS_33")),
+        Subsignal("clk_p",   Pins("E10")),
+        Subsignal("clk_n",   Pins("D10")),
+        Subsignal("data0_p", Pins("D9")),
+        Subsignal("data0_n", Pins("D8")),
+        Subsignal("data1_p", Pins("C9")),
+        Subsignal("data1_n", Pins("B9")),
+        Subsignal("data2_p", Pins("A9")),
+        Subsignal("data2_n", Pins("A8")),
+        IOStandard("TMDS_33"),
     ),
 
     # PCIe
@@ -176,26 +177,26 @@
 
     # 3.3V
     ("HR_IO", {
-        0    : "D19",
-        1    : "D18",
-        2    : "C21",
-        3    : "D20",
-        4    : "C22",
-        5    : "D21",
-        6    : "C24",
-        7    : "D23",
-        8    : "D24",
-        9    : "A19",
-        10   : "B19",
-        11   : "A20",
-        12   : "B20",
-        13   : "B21",
-        14   : "A23",
-        15   : "A24",
-        16   : "B25",
-        17   : "B26",
-        18   : "C26",
-        19   : "D25",
+        0  : "D19",
+        1  : "D18",
+        2  : "C21",
+        3  : "D20",
+        4  : "C22",
+        5  : "D21",
+        6  : "C24",
+        7  : "D23",
+        8  : "D24",
+        9  : "A19",
+        10 : "B19",
+        11 : "A20",
+        12 : "B20",
+        13 : "B21",
+        14 : "A23",
+        15 : "A24",
+        16 : "B25",
+        17 : "B26",
+        18 : "C26",
+        19 : "D25",
     }),
 
     # 3.3V
@@ -231,13 +232,14 @@ def __init__(self):
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 """)
-        self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
+        self.toolchain.bitstream_commands  = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
         self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 
     def create_programmer(self):
         return OpenOCD("openocd_xc7_ft4232.cfg", "bscan_spi_xc7k70t.bit")
 
     def do_finalize(self, fragment):
         Xilinx7SeriesPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk50",         0, loose=True), 1e9/50e6)
         self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
         self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6)
diff --git a/litex_boards/targets/aliexpress_xc7k70t.py b/litex_boards/targets/aliexpress_xc7k70t.py
@@ -60,7 +60,6 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=100e6, sdram_rate="1:1",
         with_hdmi              = False,
         with_ethernet          = False,
-        with_jtagbone          = False,
         with_pcie              = False,
         with_sdram             = True,
         with_led_chaser        = True,
@@ -99,10 +98,6 @@ def __init__(self, sys_clk_freq=100e6, sdram_rate="1:1",
             if with_video_framebuffer:
                 self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
 
-        # Jtagbone ---------------------------------------------------------------------------------
-        if with_jtagbone:
-            self.add_jtagbone()
-
         # Ethernet / Etherbone ---------------------------------------------------------------------
         if with_ethernet:
             self.ethphy = LiteEthPHYRGMII(
@@ -131,16 +126,15 @@ def __init__(self, sys_clk_freq=100e6, sdram_rate="1:1",
 def main():
     from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=aliexpress_xc7k70t.Platform, description="LiteX SoC on AliExpress XC7K70T PCIe board.")
-    parser.add_target_argument("--sys-clk-freq", default=90e6, type=float, help="System clock frequency.")
-    parser.add_target_argument("--sdram-rate",   default="1:1",             help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
-    parser.add_argument("--with-ethernet",  action="store_true", help="Enable ethernet")
-    parser.add_argument("--with-jtagbone",  action="store_true", help="Enable JTAGbone")
-    parser.add_argument("--with-pcie",  action="store_true", help="Enable PCIe")
-    parser.add_argument("--with-hdmi",  action="store_true", help="Enable HDMI")
+    parser.add_target_argument("--sys-clk-freq",    default=90e6, type=float,  help="System clock frequency.")
+    parser.add_target_argument("--sdram-rate",      default="1:1",             help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
+    parser.add_argument("--with-ethernet",          action="store_true",       help="Enable ethernet")
+    parser.add_argument("--with-pcie",              action="store_true",       help="Enable PCIe")
+    parser.add_argument("--with-hdmi",              action="store_true",       help="Enable HDMI")
     viopts = parser.target_group.add_mutually_exclusive_group()
-    viopts.add_argument("--with-video-terminal",    action="store_true", help="Enable Video Terminal (HDMI).")
-    viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
-    viopts.add_argument("--with-video-colorbars",   action="store_true", help="Enable Video Colorbars (HDMI).")
+    viopts.add_argument("--with-video-terminal",    action="store_true",       help="Enable Video Terminal (HDMI).")
+    viopts.add_argument("--with-video-framebuffer", action="store_true",       help="Enable Video Framebuffer (HDMI).")
+    viopts.add_argument("--with-video-colorbars",   action="store_true",       help="Enable Video Colorbars (HDMI).")
     args = parser.parse_args()
 
     # Note: baudrate is fixed because regardless of USB->TTL baud, the AVR <-> FPGA baudrate is
@@ -150,7 +144,6 @@ def main():
         sdram_rate             = args.sdram_rate,
         with_ethernet          = args.with_ethernet,
         with_pcie              = args.with_pcie,
-        with_jtagbone          = args.with_jtagbone,
         with_hdmi              = args.with_hdmi,
         with_video_terminal    = args.with_video_terminal,
         with_video_framebuffer = args.with_video_framebuffer,