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targets/lattice_crosslink_nx_evn: add main_ram section for firmware #524

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merged 2 commits into from
Aug 28, 2023
Merged

targets/lattice_crosslink_nx_evn: add main_ram section for firmware #524

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a5a6a31
targets/lattice_crosslink_nx_evn: add main_ram section for firmware
josuah Aug 18, 2023
232e829
Merge branch 'master' into crosslink_nx_main_ram
enjoy-digital Aug 28, 2023
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16 changes: 10 additions & 6 deletions litex_boards/targets/lattice_crosslink_nx_evn.py
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Original file line number Diff line number Diff line change
Expand Up @@ -63,10 +63,12 @@ def __init__(self, platform, sys_clk_freq):

class BaseSoC(SoCCore):
mem_map = {
"rom" : 0x00000000,
"sram" : 0x40000000,
"csr" : 0xf0000000,
"rom" : 0x00000000,
"sram" : 0x40000000,
"main_ram" : 0x60000000,
"csr" : 0xf0000000,
}

def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant",
with_led_chaser = True,
with_spi_flash = False,
Expand All @@ -85,9 +87,11 @@ def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radi
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)

# 128KB LRAM (used as SRAM) ---------------------------------------------------------------
size = 128*kB
self.spram = NXLRAM(32, size)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=size))
self.spram = NXLRAM(32, 64*kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB))

self.main_ram = NXLRAM(32, 64*kB)
self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB))

# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
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