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machdyne: fix typos; add vanille and lakritz #593

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merged 4 commits into from
Jun 22, 2024

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machdyne
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This PR fixes some typos in the Machdyne platform files and adds support for the Vanille and Lakritz FPGA computers.


def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Lakritz")
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Please switch to LiteXArgumentParser

@trabucayre
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Looks good.
Vanille board seems to have a problem with CI because it has no serial interface. It's maybe required to add a valenty USB instance or to disable uart interface.

@trabucayre trabucayre merged commit f8d41e8 into litex-hub:master Jun 22, 2024
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@trabucayre
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Applied with a small fix. Thanks @machdyne !

@machdyne
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Thanks @trabucayre !

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3 participants