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Add support for Alibaba VU13P #630

Merged
merged 1 commit into from
Dec 18, 2024
Merged

Add support for Alibaba VU13P #630

merged 1 commit into from
Dec 18, 2024

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FlyGoat
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@FlyGoat FlyGoat commented Dec 16, 2024

Alibaba VU13P board was designed for Alibaba Cloud FPGA instance and DPUs.

Those boards are appearing in used market (about 5000 CNY) and hobbyists managed to reverse engineering pinout.

PCIe, DDR, Ethernet were all tested to be working.

Note that ethernet depends on: enjoy-digital/liteeth#178

Boot log with etherbone:


        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Dec 16 2024 16:01:22
 BIOS CRC passed (f5b548c8)

 LiteX git sha1: ec06bf595

--=============== SoC ==================--
CPU:            VexRiscv @ 125MHz
BUS:            wishbone 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128.0KiB
SRAM:           8.0KiB
L2:             8.0KiB
SDRAM:          4.5GiB 72-bit @ 1000MT/s (CL-9 CWL-9)
MAIN-RAM:       1.0GiB

--========== Initialization ============--

Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
  tCK equivalent taps: 604
  Cmd/Clk scan (0-302)
  |00000  |000001111  |111111111  |111111111| best: 321
  Setting Cmd/Clk delay to 321 taps.
  Data scan:
  m0: |00001111111111111111110| delay: 60
  m1: |00000011111111111111111| delay: 88
  m2: |00111111111111111110000| delay: 17
  m3: |00111111111111111111000| delay: 18
  m4: |11111111111111111000000| delay: 00
  m5: |11111111111111111100000| delay: 00
  m6: |11111111111111000000000| delay: 00
  m7: |11111111111111000000000| delay: 00
  m8: |00000111111111111111111| delay: 80
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6 m8:6 
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |00000000000000000000000000000000| delays: -
  m0, b02: |00000000000000000000000000000000| delays: -
  m0, b03: |11111111110000000000000000000000| delays: 79+-79
  m0, b04: |00000000000000111111111111111000| delays: 334+-116
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b04 delays: 334+-117
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |00000000000000000000000000000000| delays: -
  m1, b02: |00000000000000000000000000000000| delays: -
  m1, b03: |11111111111000000000000000000000| delays: 87+-87
  m1, b04: |00000000000000011111111111111100| delays: 353+-112
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00000000000000000000000000000000| delays: -
  m1, b07: |00000000000000000000000000000000| delays: -
  best: m1, b04 delays: 353+-112
  m2, b00: |00000000000000000000000000000000| delays: -
  m2, b01: |00000000000000000000000000000000| delays: -
  m2, b02: |00000000000000000000000000000000| delays: -
  m2, b03: |11111111111111000000000000000000| delays: 110+-110
  m2, b04: |00000000000000000011111111111111| delays: 396+-115
  m2, b05: |00000000000000000000000000000000| delays: -
  m2, b06: |00000000000000000000000000000000| delays: -
  m2, b07: |00000000000000000000000000000000| delays: -
  best: m2, b04 delays: 396+-115
  m3, b00: |00000000000000000000000000000000| delays: -
  m3, b01: |00000000000000000000000000000000| delays: -
  m3, b02: |00000000000000000000000000000000| delays: -
  m3, b03: |11111111111110000000000000000000| delays: 93+-93
  m3, b04: |00000000000000000011111111111110| delays: 384+-106
  m3, b05: |00000000000000000000000000000000| delays: -
  m3, b06: |00000000000000000000000000000000| delays: -
  m3, b07: |00000000000000000000000000000000| delays: -
  best: m3, b04 delays: 380+-103
  m4, b00: |00000000000000000000000000000000| delays: -
  m4, b01: |00000000000000000000000000000000| delays: -
  m4, b02: |00000000000000000000000000000000| delays: -
  m4, b03: |11111111111111000000000000000000| delays: 106+-106
  m4, b04: |00000000000000000011111111111111| delays: 398+-107
  m4, b05: |00000000000000000000000000000000| delays: -
  m4, b06: |00000000000000000000000000000000| delays: -
  m4, b07: |00000000000000000000000000000000| delays: -
  best: m4, b04 delays: 395+-109
  m5, b00: |00000000000000000000000000000000| delays: -
  m5, b01: |00000000000000000000000000000000| delays: -
  m5, b02: |00000000000000000000000000000000| delays: -
  m5, b03: |00111111111111110000000000000000| delays: 134+-117
  m5, b04: |00000000000000000000011111111111| delays: 415+-95
  m5, b05: |00000000000000000000000000000000| delays: -
  m5, b06: |00000000000000000000000000000000| delays: -
  m5, b07: |00000000000000000000000000000000| delays: -
  best: m5, b03 delays: 136+-118
  m6, b00: |00000000000000000000000000000000| delays: -
  m6, b01: |00000000000000000000000000000000| delays: -
  m6, b02: |00000000000000000000000000000000| delays: -
  m6, b03: |00001111111111111110000000000000| delays: 172+-111
  m6, b04: |00000000000000000000000111111111| delays: 439+-71
  m6, b05: |00000000000000000000000000000000| delays: -
  m6, b06: |00000000000000000000000000000000| delays: -
  m6, b07: |00000000000000000000000000000000| delays: -
  best: m6, b03 delays: 168+-111
  m7, b00: |00000000000000000000000000000000| delays: -
  m7, b01: |00000000000000000000000000000000| delays: -
  m7, b02: |10000000000000000000000000000000| delays: -
  m7, b03: |00000111111111111110000000000000| delays: 182+-114
  m7, b04: |00000000000000000000000011111111| delays: 444+-66
  m7, b05: |00000000000000000000000000000000| delays: -
  m7, b06: |00000000000000000000000000000000| delays: -
  m7, b07: |00000000000000000000000000000000| delays: -
  best: m7, b03 delays: 181+-111
  m8, b00: |00000000000000000000000000000000| delays: -
  m8, b01: |00000000000000000000000000000000| delays: -
  m8, b02: |00000000000000000000000000000000| delays: -
  m8, b03: |11111111100000000000000000000000| delays: 63+-63
  m8, b04: |00000000000011111111111111100000| delays: 305+-119
  m8, b05: |00000000000000000000000000000001| delays: 504+-07
  m8, b06: |00000000000000000000000000000000| delays: -
  m8, b07: |00000000000000000000000000000000| delays: -
  best: m8, b04 delays: 304+-119
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB     
   Read: 0x40000000-0x40200000 2.0MiB     
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 109.3MiB/s
   Read speed: 93.7MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>

@FlyGoat
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FlyGoat commented Dec 16, 2024

Document made by hobbyists circulating in group chats.
VU13P加速卡国产U250.pdf

Example Projects: https://github.com/maswx/vu13p

@FlyGoat
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FlyGoat commented Dec 16, 2024

Note that this board actually comes with 72-bit DDR, extra bits are meant for ECC, but I haven't figured out how to enable ECC for LiteDRAM here.

@enjoy-digital
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Nice hardware, thanks @FlyGoat for the PR! We can already merge it. For ECC, that's possible support is currently only implemented in the litedram_gen.py generator: https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py#L688-L703, the idea is to have the controller using the 72-bit and have a LiteDRAMNativePortECC module in between controller and user native port (with reduced width but ECC). I could probably more help if that's not clear and if you want to go further on this.

@enjoy-digital enjoy-digital merged commit 8e00ca6 into litex-hub:master Dec 18, 2024
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@FlyGoat @enjoy-digital