Remove RISCVLoadStoreOptimizer

This will be added in a separate commit.
llvm · Jan 15, 2025 · 16f53d9 · 16f53d9
1 parent 524e5a7
commit 16f53d9
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Showing 8 changed files with 1 addition and 937 deletions.
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -48,7 +48,6 @@ add_llvm_target(RISCVCodeGen
   RISCVISelLowering.cpp
   RISCVLandingPadSetup.cpp
   RISCVMachineFunctionInfo.cpp
-  RISCVLoadStoreOptimizer.cpp
   RISCVMergeBaseOffset.cpp
   RISCVOptWInstrs.cpp
   RISCVPostRAExpandPseudoInsts.cpp

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2738,46 +2738,6 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
       .setMIFlags(MemI.getFlags());
 }
 
-bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
-  switch (Opc) {
-  default:
-    return false;
-  case RISCV::SH:
-  case RISCV::LH:
-  case RISCV::LHU:
-  case RISCV::SW:
-  case RISCV::FSW:
-  case RISCV::LW:
-  case RISCV::FLW:
-  case RISCV::SD:
-  case RISCV::FSD:
-  case RISCV::LD:
-  case RISCV::FLD:
-    return true;
-  }
-}
-
-bool RISCVInstrInfo::isLdStSafeToPair(const MachineInstr &LdSt,
-                                      const TargetRegisterInfo *TRI) {
-  // If this is a volatile load/store, don't mess with it.
-  if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3)
-    return false;
-
-  if (LdSt.getOperand(1).isFI())
-    return true;
-
-  assert(LdSt.getOperand(1).isReg() && "Expected a reg operand.");
-  // Can't cluster if the instruction modifies the base register
-  // or it is update form. e.g. ld x5,8(x5)
-  if (LdSt.modifiesRegister(LdSt.getOperand(1).getReg(), TRI))
-    return false;
-
-  if (!LdSt.getOperand(2).isImm())
-    return false;
-
-  return true;
-}
-
 bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
     const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
     int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -301,12 +301,6 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
   std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
   analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
 
-  /// Return true if pairing the given load or store may be paired with another.
-  static bool isPairableLdStInstOpc(unsigned Opc);
-
-  static bool isLdStSafeToPair(const MachineInstr &LdSt,
-                               const TargetRegisterInfo *TRI);
-
 protected:
   const RISCVSubtarget &STI;