[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

Previously we returned i32 on RV32 and i64 on RV64. The instructions only consume 32 bits and only produce 32 bits. For RV64, the result is sign extended to 64 bits like *W instructions. This patch removes this detail from the interface to improve portability and consistency. This matches the proposal for scalar intrinsics here riscv-non-isa/riscv-c-api-doc#44 I've included IR autoupgrade support as well. I'll be doing this for other builtins/intrinsics that currently use 'long' in other patches. Reviewed By: VincentWu Differential Revision: https://reviews.llvm.org/D154647
llvm · Jul 17, 2023 · a64b3e9 · a64b3e9
1 parent baba13e
commit a64b3e9
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Showing 25 changed files with 544 additions and 281 deletions.
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -61,10 +61,10 @@ TARGET_BUILTIN(__builtin_riscv_aes64es_64, "UWiUWiUWi", "nc", "zkne,64bit")
 TARGET_BUILTIN(__builtin_riscv_aes64esm_64, "UWiUWiUWi", "nc", "zkne,64bit")
 
 // Zknh extension
-TARGET_BUILTIN(__builtin_riscv_sha256sig0, "ULiULi", "nc", "zknh")
-TARGET_BUILTIN(__builtin_riscv_sha256sig1, "ULiULi", "nc", "zknh")
-TARGET_BUILTIN(__builtin_riscv_sha256sum0, "ULiULi", "nc", "zknh")
-TARGET_BUILTIN(__builtin_riscv_sha256sum1, "ULiULi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sig0, "UiUi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sig1, "UiUi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sum0, "UiUi", "nc", "zknh")
+TARGET_BUILTIN(__builtin_riscv_sha256sum1, "UiUi", "nc", "zknh")
 
 TARGET_BUILTIN(__builtin_riscv_sha512sig0h_32, "UiUiUi", "nc", "zknh,32bit")
 TARGET_BUILTIN(__builtin_riscv_sha512sig0l_32, "UiUiUi", "nc", "zknh,32bit")
@@ -78,12 +78,12 @@ TARGET_BUILTIN(__builtin_riscv_sha512sum0_64, "UWiUWi", "nc", "zknh,64bit")
 TARGET_BUILTIN(__builtin_riscv_sha512sum1_64, "UWiUWi", "nc", "zknh,64bit")
 
 // Zksed extension
-TARGET_BUILTIN(__builtin_riscv_sm4ed, "ULiULiULiIUi", "nc", "zksed")
-TARGET_BUILTIN(__builtin_riscv_sm4ks, "ULiULiULiIUi", "nc", "zksed")
+TARGET_BUILTIN(__builtin_riscv_sm4ed, "UiUiUiIUi", "nc", "zksed")
+TARGET_BUILTIN(__builtin_riscv_sm4ks, "UiUiUiIUi", "nc", "zksed")
 
 // Zksh extension
-TARGET_BUILTIN(__builtin_riscv_sm3p0, "ULiULi", "nc", "zksh")
-TARGET_BUILTIN(__builtin_riscv_sm3p1, "ULiULi", "nc", "zksh")
+TARGET_BUILTIN(__builtin_riscv_sm3p0, "UiUi", "nc", "zksh")
+TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
 
 // Zihintntl extension
 TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "experimental-zihintntl")

diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -20265,39 +20265,31 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   // Zknh
   case RISCV::BI__builtin_riscv_sha256sig0:
     ID = Intrinsic::riscv_sha256sig0;
-    IntrinsicTypes = {ResultType};
     break;
   case RISCV::BI__builtin_riscv_sha256sig1:
     ID = Intrinsic::riscv_sha256sig1;
-    IntrinsicTypes = {ResultType};
     break;
   case RISCV::BI__builtin_riscv_sha256sum0:
     ID = Intrinsic::riscv_sha256sum0;
-    IntrinsicTypes = {ResultType};
     break;
   case RISCV::BI__builtin_riscv_sha256sum1:
     ID = Intrinsic::riscv_sha256sum1;
-    IntrinsicTypes = {ResultType};
     break;
 
   // Zksed
   case RISCV::BI__builtin_riscv_sm4ks:
     ID = Intrinsic::riscv_sm4ks;
-    IntrinsicTypes = {ResultType};
     break;
   case RISCV::BI__builtin_riscv_sm4ed:
     ID = Intrinsic::riscv_sm4ed;
-    IntrinsicTypes = {ResultType};
     break;
 
   // Zksh
   case RISCV::BI__builtin_riscv_sm3p0:
     ID = Intrinsic::riscv_sm3p0;
-    IntrinsicTypes = {ResultType};
     break;
   case RISCV::BI__builtin_riscv_sm3p1:
     ID = Intrinsic::riscv_sm3p1;
-    IntrinsicTypes = {ResultType};
     break;
 
   // Zihintntl

diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
@@ -9,10 +9,10 @@
 // RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig0.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig0(i32 [[TMP0]])
 // RV32ZKNH-NEXT:    ret i32 [[TMP1]]
 //
-unsigned long sha256sig0(unsigned long rs1) {
+uint32_t sha256sig0(uint32_t rs1) {
   return __builtin_riscv_sha256sig0(rs1);
 }
 
@@ -21,10 +21,10 @@ unsigned long sha256sig0(unsigned long rs1) {
 // RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig1.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig1(i32 [[TMP0]])
 // RV32ZKNH-NEXT:    ret i32 [[TMP1]]
 //
-unsigned long sha256sig1(unsigned long rs1) {
+uint32_t sha256sig1(uint32_t rs1) {
   return __builtin_riscv_sha256sig1(rs1);
 }
 
@@ -33,10 +33,10 @@ unsigned long sha256sig1(unsigned long rs1) {
 // RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum0.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum0(i32 [[TMP0]])
 // RV32ZKNH-NEXT:    ret i32 [[TMP1]]
 //
-unsigned long sha256sum0(unsigned long rs1) {
+uint32_t sha256sum0(uint32_t rs1) {
   return __builtin_riscv_sha256sum0(rs1);
 }
 
@@ -45,10 +45,10 @@ unsigned long sha256sum0(unsigned long rs1) {
 // RV32ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
 // RV32ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum1.i32(i32 [[TMP0]])
+// RV32ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum1(i32 [[TMP0]])
 // RV32ZKNH-NEXT:    ret i32 [[TMP1]]
 //
-unsigned long sha256sum1(unsigned long rs1) {
+uint32_t sha256sum1(uint32_t rs1) {
   return __builtin_riscv_sha256sum1(rs1);
 }
 

diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
@@ -58,49 +58,49 @@ uint64_t sha512sum1(uint64_t rs1) {
 
 // RV64ZKNH-LABEL: @sha256sig0(
 // RV64ZKNH-NEXT:  entry:
-// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
-// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
-// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
-// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sig0.i64(i64 [[TMP0]])
-// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig0(i32 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i32 [[TMP1]]
 //
-uint64_t sha256sig0(uint64_t rs1) {
+uint32_t sha256sig0(uint32_t rs1) {
   return __builtin_riscv_sha256sig0(rs1);
 }
 
 // RV64ZKNH-LABEL: @sha256sig1(
 // RV64ZKNH-NEXT:  entry:
-// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
-// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
-// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
-// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sig1.i64(i64 [[TMP0]])
-// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sig1(i32 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i32 [[TMP1]]
 //
-uint64_t sha256sig1(uint64_t rs1) {
+uint32_t sha256sig1(uint32_t rs1) {
   return __builtin_riscv_sha256sig1(rs1);
 }
 
 
 // RV64ZKNH-LABEL: @sha256sum0(
 // RV64ZKNH-NEXT:  entry:
-// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
-// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
-// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
-// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sum0.i64(i64 [[TMP0]])
-// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum0(i32 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i32 [[TMP1]]
 //
-uint64_t sha256sum0(uint64_t rs1) {
+uint32_t sha256sum0(uint32_t rs1) {
   return __builtin_riscv_sha256sum0(rs1);
 }
 
 // RV64ZKNH-LABEL: @sha256sum1(
 // RV64ZKNH-NEXT:  entry:
-// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
-// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
-// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
-// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha256sum1.i64(i64 [[TMP0]])
-// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sha256sum1(i32 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i32 [[TMP1]]
 //
-uint64_t sha256sum1(uint64_t rs1) {
+uint32_t sha256sum1(uint32_t rs1) {
   return __builtin_riscv_sha256sum1(rs1);
 }
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
diff --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
@@ -0,0 +1,59 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zksed -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZKSED
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zksed -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZKSED
+
+#include <stdint.h>
+
+// RV32ZKSED-LABEL: @sm4ks(
+// RV32ZKSED-NEXT:  entry:
+// RV32ZKSED-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ks(i32 [[TMP0]], i32 [[TMP1]], i32 0)
+// RV32ZKSED-NEXT:    ret i32 [[TMP2]]
+//
+// RV64ZKSED-LABEL: @sm4ks(
+// RV64ZKSED-NEXT:  entry:
+// RV64ZKSED-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKSED-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKSED-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZKSED-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
+// RV64ZKSED-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZKSED-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
+// RV64ZKSED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ks(i32 [[TMP0]], i32 [[TMP1]], i32 0)
+// RV64ZKSED-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t sm4ks(uint32_t rs1, uint32_t rs2) {
+  return __builtin_riscv_sm4ks(rs1, rs2, 0);
+}
+
+// RV32ZKSED-LABEL: @sm4ed(
+// RV32ZKSED-NEXT:  entry:
+// RV32ZKSED-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV32ZKSED-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
+// RV32ZKSED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ed(i32 [[TMP0]], i32 [[TMP1]], i32 0)
+// RV32ZKSED-NEXT:    ret i32 [[TMP2]]
+//
+// RV64ZKSED-LABEL: @sm4ed(
+// RV64ZKSED-NEXT:  entry:
+// RV64ZKSED-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKSED-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
+// RV64ZKSED-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZKSED-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
+// RV64ZKSED-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZKSED-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
+// RV64ZKSED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.sm4ed(i32 [[TMP0]], i32 [[TMP1]], i32 0)
+// RV64ZKSED-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t sm4ed(uint32_t rs1, uint32_t rs2) {
+  return __builtin_riscv_sm4ed(rs1, rs2, 0);
+}