[win/asan] GetInstructionSize: Support some more 10 or more byte inst…

…ructions. This patch adds several instructions seen when trying to run a executable built with ASan with llvm-mingw. (x86 and x86_64, using the git tip in llvm-project). Also includes instructions collected by Roman Pišl and Eric Pouech in the Wine bug reports below. Fixes: #96270 Co-authored-by: Roman Pišl <[email protected]> https://bugs.winehq.org/show_bug.cgi?id=50993 https://bugs.winehq.org/attachment.cgi?id=70233 Co-authored-by: Eric Pouech <[email protected]> https://bugs.winehq.org/show_bug.cgi?id=52386 https://bugs.winehq.org/attachment.cgi?id=71626
llvm · Dec 1, 2024 · c12c753 · c12c753
1 parent cb33c23
commit c12c753
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diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
@@ -741,6 +741,8 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
     case 0x7B81:  // 81 7B YY XX XX XX XX  cmp DWORD PTR [rbx+YY], XX XX XX XX
     case 0x7981:  // 81 79 YY XX XX XX XX  cmp dword ptr [rcx+YY], XX XX XX XX
       return 7;
+    case 0xb848:  // 48 b8 XX XX XX XX XX XX XX XX : movabs rax, XX XX XX XX XX XX XX XX
+      return 10;
   }
 
   switch (0x00FFFFFF & *(u32 *)address) {
@@ -916,6 +918,18 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
       return 5;
   }
 
+//  switch (0xFFFFFFFFFFFFULL & *(u64*)(address)) {
+//    case 0x841f0f2e6666:  // 66 66 2e 0f 1f 84 YY XX XX XX XX
+//                          // data16 cs nop WORD PTR [rax+rax*1 + XX XX XX XX]
+//      return 11;
+//  }
+//
+//  switch (*(u64*)(address)) {
+//    case 0x841f0f2e66666666:  // 66 66 66 66 2e 0f 1f 84 YY XX XX XX XX
+//                              // data16 data16 data16 cs nop WORD PTR [rax+rax*1 + XX XX XX XX]
+//      return 13;
+//  }
+
 #else
 
   switch (*(u8*)address) {

diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -1066,6 +1066,9 @@ const struct InstructionSizeData {
     { 8, {0xc7, 0x44, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "C7 44 24 XX YY YY YY YY : mov dword ptr [rsp + XX], YYYYYYYY"},
     { 9, {0x41, 0x81, 0x7c, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "41 81 7c ZZ YY XX XX XX XX : cmp DWORD PTR [reg+reg*n+YY], XX XX XX XX"},
     { 9, {0xA1, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "A1 XX XX XX XX XX XX XX XX : movabs eax, dword ptr ds:[XXXXXXXX]"},
+    {10, {0x48, 0xb8, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79}, 0, "48 b8 XX XX XX XX XX XX XX XX : movabs rax,XX XX XX XX XX XX XX XX"},
+//    {11, {0x66, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x76, 0x77, 0x78, 0x79, 0x70}, 0, "66 66 2e 0f 1f 84 YY XX XX XX XX : data16 cs nop WORD PTR [rax+rax*1 + XX XX XX XX]"},
+//    {13, {0x66, 0x66, 0x66, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x78, 0x79, 0x70, 0x71, 0x72}, 0, "66 66 66 66 2e 0f 1f 84 YY XX XX XX XX : data16 data16 data16 cs nop WORD PTR [rax+rax*1 + XX XX XX XX]"},
 #else
     // sorted list
     { 3, {0x8B, 0x45, 0x72}, 0, "8B 45 XX : mov eax, dword ptr [ebp + XX]"},