[M68k] implement move to and from sr #111145
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-m68k Author: Janis Heims (TechnoElf) ChangesThis PR enables the use of the status register in inline assembly. Full diff: https://github.com/llvm/llvm-project/pull/111145.diff 4 Files Affected:
diff --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
index 126176133dc027..31583eba658462 100644
--- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
@@ -258,6 +258,7 @@ static inline unsigned getRegisterIndex(unsigned Register) {
// We don't care about the indices of these registers.
case M68k::PC:
case M68k::CCR:
+ case M68k::SR:
case M68k::FPC:
case M68k::FPS:
case M68k::FPIAR:
@@ -636,10 +637,13 @@ bool M68kAsmParser::parseRegisterName(MCRegister &RegNo, SMLoc Loc,
StringRef RegisterName) {
auto RegisterNameLower = RegisterName.lower();
- // CCR register
+ // CCR and SR register
if (RegisterNameLower == "ccr") {
RegNo = M68k::CCR;
return true;
+ } else if (RegisterNameLower == "sr") {
+ RegNo = M68k::SR;
+ return true;
}
// Parse simple general-purpose registers.
diff --git a/llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp b/llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
index 7f0f737faccd0d..43120d8cdef1ee 100644
--- a/llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
+++ b/llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
@@ -111,6 +111,12 @@ static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn,
llvm_unreachable("unimplemented");
}
+static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst, APInt &Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ llvm_unreachable("unimplemented");
+}
+
static DecodeStatus DecodeImm32(MCInst &Inst, uint64_t Imm, uint64_t Address,
const void *Decoder) {
Inst.addOperand(MCOperand::createImm(M68k::swapWord<uint32_t>(Imm)));
diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
index dc777a933e2786..5f5cbfbc55ce15 100644
--- a/llvm/lib/Target/M68k/M68kInstrData.td
+++ b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -365,13 +365,14 @@ def MOVM32mp_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.POp>;
// ons that will be resolved sometime after RA pass.
//===----------------------------------------------------------------------===//
+/// Move to CCR
/// --------------------------------------------------
/// F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
/// --------------------------------------------------
/// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 1 0 0 1 1 | MODE | REG
/// --------------------------------------------------
-let Defs = [CCR] in
+let Defs = [CCR] in {
class MxMoveToCCR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
: MxInst<(outs CCRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
let Inst = (ascend
@@ -382,6 +383,7 @@ class MxMoveToCCR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
class MxMoveToCCRPseudo<MxOperand MEMOp>
: MxPseudo<(outs CCRC:$dst), (ins MEMOp:$src)>;
+} // let Defs = [CCR]
let mayLoad = 1 in
foreach AM = MxMoveSupportedAMs in {
@@ -434,6 +436,64 @@ foreach AM = MxMoveSupportedAMs in {
def MOV16dc : MxMoveFromCCR_R;
def MOV8dc : MxMoveFromCCRPseudo<MxOp8AddrMode_d.Op>;
+/// Move to SR
+/// --------------------------------------------------
+/// F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
+/// --------------------------------------------------
+/// | EFFECTIVE ADDRESS
+/// 0 1 0 0 0 1 1 0 1 1 | MODE | REG
+/// --------------------------------------------------
+let Defs = [SR] in {
+class MxMoveToSR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
+ : MxInst<(outs SRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
+ let Inst = (ascend
+ (descend 0b0100011011, SRC_ENC.EA),
+ SRC_ENC.Supplement
+ );
+}
+} // let Defs = [SR]
+
+let mayLoad = 1 in
+foreach AM = MxMoveSupportedAMs in {
+ def MOV16s # AM : MxMoveToSR<!cast<MxOpBundle>("MxOp16AddrMode_"#AM).Op,
+ !cast<MxEncMemOp>("MxMoveSrcOpEnc_"#AM)>;
+} // foreach AM
+
+def MOV16sd : MxMoveToSR<MxOp16AddrMode_d.Op, MxMoveSrcOpEnc_d>;
+
+/// Move from SR
+/// --------------------------------------------------
+/// F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
+/// --------------------------------------------------
+/// | EFFECTIVE ADDRESS
+/// 0 1 0 0 0 0 0 0 1 1 | MODE | REG
+/// --------------------------------------------------
+let Uses = [SR] in {
+class MxMoveFromSR_R
+ : MxInst<(outs MxDRD16:$dst), (ins SRC:$src), "move.w\t$src, $dst", []>,
+ Requires<[ AtLeastM68010 ]> {
+ let Inst = (descend 0b0100000011, MxEncAddrMode_d<"dst">.EA);
+}
+
+class MxMoveFromSR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
+ : MxInst<(outs), (ins MEMOp:$dst, SRC:$src), "move.w\t$src, $dst", []>,
+ Requires<[ AtLeastM68010 ]> {
+ let Inst = (ascend
+ (descend 0b0100000011, DST_ENC.EA),
+ DST_ENC.Supplement
+ );
+}
+} // let Uses = [SR]
+
+let mayStore = 1 in
+foreach AM = MxMoveSupportedAMs in {
+ def MOV16 # AM # s
+ : MxMoveFromSR_M<!cast<MxOpBundle>("MxOp16AddrMode_"#AM).Op,
+ !cast<MxEncMemOp>("MxMoveDstOpEnc_"#AM)>;
+} // foreach AM
+
+def MOV16ds : MxMoveFromSR_R;
+
//===----------------------------------------------------------------------===//
// LEA
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/M68k/inline-asm.ll b/llvm/test/CodeGen/M68k/inline-asm.ll
index dda943920788d4..70e2d16ac1844b 100644
--- a/llvm/test/CodeGen/M68k/inline-asm.ll
+++ b/llvm/test/CodeGen/M68k/inline-asm.ll
@@ -152,3 +152,26 @@ entry:
ret void
}
+define void @move_sr_ccr() {
+; CHECK-LABEL: move_sr_ccr:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0:
+; CHECK-NEXT: ;APP
+; CHECK-NEXT: move.w %sr, %d0
+; CHECK-NEXT: ;NO_APP
+; CHECK-NEXT: ;APP
+; CHECK-NEXT: move.w %d0, %sr
+; CHECK-NEXT: ;NO_APP
+; CHECK-NEXT: ;APP
+; CHECK-NEXT: move.w %ccr, %d0
+; CHECK-NEXT: ;NO_APP
+; CHECK-NEXT: ;APP
+; CHECK-NEXT: move.w %d0, %ccr
+; CHECK-NEXT: ;NO_APP
+; CHECK-NEXT: rts
+ %1 = call i16 asm sideeffect "move.w %sr, $0", "=r"()
+ call void asm sideeffect "move.w $0, %sr", "r"(i16 %1)
+ %2 = call i16 asm sideeffect "move.w %ccr, $0", "=r"()
+ call void asm sideeffect "move.w $0, %ccr", "r"(i16 %2)
+ ret void
+}
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Ping @0x59616e @mshockwave |
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@TechnoElf I just ran in to the need for this, are you planning to revisit? Happy to add more tests on top of your commit to get it in if you don't feel like it |
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@knickish Yeah, sorry - my priorities at work got shifted around a bit, so I haven't had the time to look into the tests further. I would definitely like to finish this up though. Currently I'm stuck on trying to figure out how to write an MC test. If you have any pointers to docs or examples, I could probably throw something together quickly. |
Understood, will make a PR against your fork then with a test if I can figure it out, and can do what you like with it |
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I've merged your test @knickish. Thanks a bunch! |
example MC test for MOVE to/from SR
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@TechnoElf Congratulations on having your first Pull Request (PR) merged into the LLVM Project! Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR. Please check whether problems have been caused by your change specifically, as the builds can include changes from many authors. It is not uncommon for your change to be included in a build that fails due to someone else's changes, or infrastructure issues. How to do this, and the rest of the post-merge process, is covered in detail here. If your change does cause a problem, it may be reverted, or you can revert it yourself. This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again. If you don't get any reports, no action is required from you. Your changes are working as expected, well done! |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/27/builds/4380 Here is the relevant piece of the build log for the reference |
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I'm currently looking into this error ^. |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/3/builds/10098 Here is the relevant piece of the build log for the reference |
This PR enables the use of the status register in inline assembly.
This is necessary to, for example, set and retrieve the current interrupt mask.