[X86] Add atomic vector tests for unaligned >1 sizes. #120387

jofrn · 2024-12-18T08:41:44Z

Unaligned atomic vectors with size >1 are lowered to calls.
Adding their tests separately here.

Stack:

⚠️ Part of a stack created by spr. Do not merge manually using the UI - doing so may have unexpected results.

llvmbot · 2024-12-18T08:42:21Z

@llvm/pr-subscribers-backend-x86

Author: None (jofrn)

Changes

Atomic vectors with size >1 are lowered to calls. Adding
their tests separately here.

Stack:

#120387 ⬅
#120386
#120385
#120384

⚠️ Part of a stack created by spr. Do not merge manually using the UI - doing so may have unexpected results.

Full diff: https://github.com/llvm/llvm-project/pull/120387.diff

1 Files Affected:

(modified) llvm/test/CodeGen/X86/atomic-load-store.ll (+223)

diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll b/llvm/test/CodeGen/X86/atomic-load-store.ll
index 2bde0d2ffd06ad..435e58bef6642d 100644
--- a/llvm/test/CodeGen/X86/atomic-load-store.ll
+++ b/llvm/test/CodeGen/X86/atomic-load-store.ll
@@ -110,3 +110,226 @@ define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
   ret <1 x bfloat> %ret
 }
 
+define <1 x i64> @atomic_vec1_i64(ptr %x) {
+; CHECK-LABEL: atomic_vec1_i64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    movq %rdi, %rsi
+; CHECK-NEXT:    movq %rsp, %rdx
+; CHECK-NEXT:    movl $8, %edi
+; CHECK-NEXT:    movl $2, %ecx
+; CHECK-NEXT:    callq ___atomic_load
+; CHECK-NEXT:    movq (%rsp), %rax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
+;
+; CHECK0-LABEL: atomic_vec1_i64:
+; CHECK0:       ## %bb.0:
+; CHECK0-NEXT:    pushq %rax
+; CHECK0-NEXT:    .cfi_def_cfa_offset 16
+; CHECK0-NEXT:    movq %rdi, %rsi
+; CHECK0-NEXT:    movl $8, %edi
+; CHECK0-NEXT:    movq %rsp, %rdx
+; CHECK0-NEXT:    movl $2, %ecx
+; CHECK0-NEXT:    callq ___atomic_load
+; CHECK0-NEXT:    movq (%rsp), %rax
+; CHECK0-NEXT:    popq %rcx
+; CHECK0-NEXT:    retq
+  %ret = load atomic <1 x i64>, ptr %x acquire, align 4
+  ret <1 x i64> %ret
+}
+
+define <1 x double> @atomic_vec1_double(ptr %x) {
+; CHECK-LABEL: atomic_vec1_double:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    movq %rdi, %rsi
+; CHECK-NEXT:    movq %rsp, %rdx
+; CHECK-NEXT:    movl $8, %edi
+; CHECK-NEXT:    movl $2, %ecx
+; CHECK-NEXT:    callq ___atomic_load
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    retq
+;
+; CHECK0-LABEL: atomic_vec1_double:
+; CHECK0:       ## %bb.0:
+; CHECK0-NEXT:    pushq %rax
+; CHECK0-NEXT:    .cfi_def_cfa_offset 16
+; CHECK0-NEXT:    movq %rdi, %rsi
+; CHECK0-NEXT:    movl $8, %edi
+; CHECK0-NEXT:    movq %rsp, %rdx
+; CHECK0-NEXT:    movl $2, %ecx
+; CHECK0-NEXT:    callq ___atomic_load
+; CHECK0-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:    popq %rax
+; CHECK0-NEXT:    retq
+  %ret = load atomic <1 x double>, ptr %x acquire, align 4
+  ret <1 x double> %ret
+}
+
+define <2 x i32> @atomic_vec2_i32(ptr %x) {
+; CHECK-LABEL: atomic_vec2_i32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    movq %rdi, %rsi
+; CHECK-NEXT:    movq %rsp, %rdx
+; CHECK-NEXT:    movl $8, %edi
+; CHECK-NEXT:    movl $2, %ecx
+; CHECK-NEXT:    callq ___atomic_load
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    retq
+;
+; CHECK0-LABEL: atomic_vec2_i32:
+; CHECK0:       ## %bb.0:
+; CHECK0-NEXT:    pushq %rax
+; CHECK0-NEXT:    .cfi_def_cfa_offset 16
+; CHECK0-NEXT:    movq %rdi, %rsi
+; CHECK0-NEXT:    movl $8, %edi
+; CHECK0-NEXT:    movq %rsp, %rdx
+; CHECK0-NEXT:    movl $2, %ecx
+; CHECK0-NEXT:    callq ___atomic_load
+; CHECK0-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:    popq %rax
+; CHECK0-NEXT:    retq
+  %ret = load atomic <2 x i32>, ptr %x acquire, align 4
+  ret <2 x i32> %ret
+}
+
+define <4 x float> @atomic_vec4_float(ptr %x) {
+; CHECK-LABEL: atomic_vec4_float:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    subq $24, %rsp
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    movq %rdi, %rsi
+; CHECK-NEXT:    movq %rsp, %rdx
+; CHECK-NEXT:    movl $16, %edi
+; CHECK-NEXT:    movl $2, %ecx
+; CHECK-NEXT:    callq ___atomic_load
+; CHECK-NEXT:    movaps (%rsp), %xmm0
+; CHECK-NEXT:    addq $24, %rsp
+; CHECK-NEXT:    retq
+;
+; CHECK0-LABEL: atomic_vec4_float:
+; CHECK0:       ## %bb.0:
+; CHECK0-NEXT:    subq $24, %rsp
+; CHECK0-NEXT:    .cfi_def_cfa_offset 32
+; CHECK0-NEXT:    movq %rdi, %rsi
+; CHECK0-NEXT:    movl $16, %edi
+; CHECK0-NEXT:    movq %rsp, %rdx
+; CHECK0-NEXT:    movl $2, %ecx
+; CHECK0-NEXT:    callq ___atomic_load
+; CHECK0-NEXT:    movaps (%rsp), %xmm0
+; CHECK0-NEXT:    addq $24, %rsp
+; CHECK0-NEXT:    retq
+  %ret = load atomic <4 x float>, ptr %x acquire, align 4
+  ret <4 x float> %ret
+}
+
+define <8 x double> @atomic_vec8_double(ptr %x) {
+; CHECK-LABEL: atomic_vec8_double:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    subq $72, %rsp
+; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    movq %rdi, %rsi
+; CHECK-NEXT:    movq %rsp, %rdx
+; CHECK-NEXT:    movl $64, %edi
+; CHECK-NEXT:    movl $2, %ecx
+; CHECK-NEXT:    callq ___atomic_load
+; CHECK-NEXT:    movaps (%rsp), %xmm0
+; CHECK-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
+; CHECK-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm2
+; CHECK-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm3
+; CHECK-NEXT:    addq $72, %rsp
+; CHECK-NEXT:    retq
+;
+; CHECK0-LABEL: atomic_vec8_double:
+; CHECK0:       ## %bb.0:
+; CHECK0-NEXT:    subq $72, %rsp
+; CHECK0-NEXT:    .cfi_def_cfa_offset 80
+; CHECK0-NEXT:    movq %rdi, %rsi
+; CHECK0-NEXT:    movl $64, %edi
+; CHECK0-NEXT:    movq %rsp, %rdx
+; CHECK0-NEXT:    movl $2, %ecx
+; CHECK0-NEXT:    callq ___atomic_load
+; CHECK0-NEXT:    movapd (%rsp), %xmm0
+; CHECK0-NEXT:    movapd {{[0-9]+}}(%rsp), %xmm1
+; CHECK0-NEXT:    movapd {{[0-9]+}}(%rsp), %xmm2
+; CHECK0-NEXT:    movapd {{[0-9]+}}(%rsp), %xmm3
+; CHECK0-NEXT:    addq $72, %rsp
+; CHECK0-NEXT:    retq
+  %ret = load atomic <8 x double>, ptr %x acquire, align 4
+  ret <8 x double> %ret
+}
+
+define <16 x bfloat> @atomic_vec16_bfloat(ptr %x) {
+; CHECK-LABEL: atomic_vec16_bfloat:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    subq $40, %rsp
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-NEXT:    movq %rdi, %rsi
+; CHECK-NEXT:    movq %rsp, %rdx
+; CHECK-NEXT:    movl $32, %edi
+; CHECK-NEXT:    movl $2, %ecx
+; CHECK-NEXT:    callq ___atomic_load
+; CHECK-NEXT:    movaps (%rsp), %xmm0
+; CHECK-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
+; CHECK-NEXT:    addq $40, %rsp
+; CHECK-NEXT:    retq
+;
+; CHECK0-LABEL: atomic_vec16_bfloat:
+; CHECK0:       ## %bb.0:
+; CHECK0-NEXT:    subq $40, %rsp
+; CHECK0-NEXT:    .cfi_def_cfa_offset 48
+; CHECK0-NEXT:    movq %rdi, %rsi
+; CHECK0-NEXT:    movl $32, %edi
+; CHECK0-NEXT:    movq %rsp, %rdx
+; CHECK0-NEXT:    movl $2, %ecx
+; CHECK0-NEXT:    callq ___atomic_load
+; CHECK0-NEXT:    movaps (%rsp), %xmm0
+; CHECK0-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
+; CHECK0-NEXT:    addq $40, %rsp
+; CHECK0-NEXT:    retq
+  %ret = load atomic <16 x bfloat>, ptr %x acquire, align 4
+  ret <16 x bfloat> %ret
+}
+
+define <32 x half> @atomic_vec32_half(ptr %x) {
+; CHECK-LABEL: atomic_vec32_half:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    subq $72, %rsp
+; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    movq %rdi, %rsi
+; CHECK-NEXT:    movq %rsp, %rdx
+; CHECK-NEXT:    movl $64, %edi
+; CHECK-NEXT:    movl $2, %ecx
+; CHECK-NEXT:    callq ___atomic_load
+; CHECK-NEXT:    movaps (%rsp), %xmm0
+; CHECK-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
+; CHECK-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm2
+; CHECK-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm3
+; CHECK-NEXT:    addq $72, %rsp
+; CHECK-NEXT:    retq
+;
+; CHECK0-LABEL: atomic_vec32_half:
+; CHECK0:       ## %bb.0:
+; CHECK0-NEXT:    subq $72, %rsp
+; CHECK0-NEXT:    .cfi_def_cfa_offset 80
+; CHECK0-NEXT:    movq %rdi, %rsi
+; CHECK0-NEXT:    movl $64, %edi
+; CHECK0-NEXT:    movq %rsp, %rdx
+; CHECK0-NEXT:    movl $2, %ecx
+; CHECK0-NEXT:    callq ___atomic_load
+; CHECK0-NEXT:    movaps (%rsp), %xmm0
+; CHECK0-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
+; CHECK0-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm2
+; CHECK0-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm3
+; CHECK0-NEXT:    addq $72, %rsp
+; CHECK0-NEXT:    retq
+  %ret = load atomic <32 x half>, ptr %x acquire, align 4
+  ret <32 x half> %ret
+}

RKSimon · 2024-12-18T10:07:53Z

llvm/test/CodeGen/X86/atomic-load-store.ll

  ret <1 x bfloat> %ret
 }

+define <1 x i64> @atomic_vec1_i64(ptr %x) {


add nounwind to get rid of cfi noise

RKSimon

LGTM - cheers

jyknight · 2024-12-18T23:11:51Z

Atomic vectors with size >1 are lowered to calls.

That's not true; they're only lowered to calls when the alignment is not known to be sufficient (e.g. <2 x i32> must have align 8, not align 4).

arsenm · 2024-12-19T01:31:19Z

llvm/test/CodeGen/X86/atomic-load-store.ll

+; CHECK0-NEXT:    movq (%rsp), %rax
+; CHECK0-NEXT:    popq %rcx
+; CHECK0-NEXT:    retq
+  %ret = load atomic <1 x ptr>, ptr %x acquire, align 4


Should test the naturally aligned case, this under-aligned one is a separate test

Added that one here: https://github.com/llvm/llvm-project/pull/120385/files.

Probably should just add these kinds of cases with that PR. The set of strange under-aligned cases happen to work now, but I'm not sure that's enough reason to separately push them

llvm/test/CodeGen/X86/atomic-load-store.ll

arsenm · 2024-12-19T04:05:06Z

llvm/test/CodeGen/X86/atomic-load-store.ll

+; CHECK0-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK0-NEXT:    popq %rax
+; CHECK0-NEXT:    retq
+  %ret = load atomic <1 x double>, ptr %x acquire, align 4


these are all under aligned

Added this one here: https://github.com/llvm/llvm-project/pull/120386/files.

Unaligned atomic vectors with size >1 are lowered to calls. Adding their tests separately here. commit-id:a06a5cc6

This was referenced Dec 18, 2024

[SelectionDAG] Legalize <1 x T> vector types for atomic load #120385

Open

IR/Verifier: Allow vector type in atomic load and store #120384

Open

[X86] Manage atomic load of fp -> int promotion in DAG #120386

Open

llvmbot added the backend:X86 label Dec 18, 2024

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from 441e75a to 3773e66 Compare December 18, 2024 08:54

RKSimon reviewed Dec 18, 2024

View reviewed changes

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from 3773e66 to 813fffe Compare December 18, 2024 11:45

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from 141279f to 70bb5b9 Compare December 18, 2024 11:45

jofrn requested review from Pierre-vh, arsenm and shiltian December 18, 2024 11:48

jofrn mentioned this pull request Dec 18, 2024

[X86] Add atomic vector tests for >1 sizes. #120316

Open

RKSimon approved these changes Dec 18, 2024

View reviewed changes

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from 70bb5b9 to dac7f1e Compare December 18, 2024 19:11

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch 2 times, most recently from 05a76cf to bb71e93 Compare December 18, 2024 20:47

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from dac7f1e to df5e28c Compare December 18, 2024 20:47

arsenm reviewed Dec 19, 2024

View reviewed changes

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from bb71e93 to 5e8da05 Compare December 19, 2024 02:29

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch 2 times, most recently from 255a011 to e3dd939 Compare December 19, 2024 02:31

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from 5e8da05 to e71ac05 Compare December 19, 2024 02:31

arsenm reviewed Dec 19, 2024

View reviewed changes

jofrn changed the title ~~[X86] Add atomic vector tests for >1 sizes.~~ [X86] Add atomic vector tests for unaligned >1 sizes. Dec 19, 2024

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from e3dd939 to b336c25 Compare December 19, 2024 13:16

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch 2 times, most recently from 0564ecb to 454b8e6 Compare December 19, 2024 16:01

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from b336c25 to 7ef2576 Compare December 19, 2024 16:01

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from 6078905 to fdc2107 Compare May 6, 2025 03:50

jofrn changed the base branch from users/jofrn/spr/main/f9d761c5 to main May 6, 2025 06:03

jofrn mentioned this pull request May 6, 2025

[X86] Remove extra MOV after widening atomic load #138635

Open

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from acfcbcc to 93e8bef Compare May 6, 2025 06:03

jofrn changed the base branch from main to users/jofrn/spr/main/f9d761c5 May 6, 2025 06:04

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from 5005b94 to c7d4433 Compare May 6, 2025 15:04

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch 2 times, most recently from a9729ee to 5ce8ea6 Compare May 7, 2025 12:53

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from c7d4433 to 531bc05 Compare May 7, 2025 12:53

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from 5ce8ea6 to 01f388d Compare May 8, 2025 01:53

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from 531bc05 to 70a0cad Compare May 8, 2025 01:53

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from 01f388d to d09c5a1 Compare May 8, 2025 23:38

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from 0219785 to e99bf25 Compare May 9, 2025 12:53

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from d09c5a1 to 315e1fc Compare May 9, 2025 12:53

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from e99bf25 to 4843957 Compare May 9, 2025 19:43

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch 2 times, most recently from 81e34f8 to 0a2f8f2 Compare May 9, 2025 20:03

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from 4843957 to 5d4d774 Compare May 9, 2025 20:03

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch 3 times, most recently from 63a3178 to d212710 Compare May 12, 2025 05:34

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from d212710 to 7b4708f Compare May 27, 2025 17:34

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from ce52d52 to 87d478c Compare May 27, 2025 17:34

jofrn changed the base branch from users/jofrn/spr/main/f9d761c5 to main June 1, 2025 20:46

jofrn mentioned this pull request Jun 1, 2025

[X86] Cast atomic vectors in IR to support floats #142320

Open

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from 7b4708f to 66ad4f4 Compare June 1, 2025 20:46

jofrn changed the base branch from main to users/jofrn/spr/main/f9d761c5 June 1, 2025 20:46

[X86] Add atomic vector tests for unaligned >1 sizes.

620e182

Unaligned atomic vectors with size >1 are lowered to calls. Adding their tests separately here. commit-id:a06a5cc6

jofrn force-pushed the users/jofrn/spr/main/a06a5cc6 branch from 66ad4f4 to 620e182 Compare June 2, 2025 04:15

jofrn force-pushed the users/jofrn/spr/main/f9d761c5 branch from 1e14381 to 9a088dc Compare June 2, 2025 04:15

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[X86] Add atomic vector tests for unaligned >1 sizes. #120387

[X86] Add atomic vector tests for unaligned >1 sizes. #120387

Uh oh!

jofrn commented Dec 18, 2024 •

edited

Loading

Uh oh!

llvmbot commented Dec 18, 2024

Uh oh!

RKSimon Dec 18, 2024

Uh oh!

RKSimon left a comment

Uh oh!

jyknight commented Dec 18, 2024

Uh oh!

arsenm Dec 19, 2024

Uh oh!

jofrn Dec 20, 2024

Uh oh!

arsenm Jan 6, 2025

Uh oh!

Uh oh!

arsenm Dec 19, 2024

Uh oh!

jofrn Dec 20, 2024

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

5 participants

[X86] Add atomic vector tests for unaligned >1 sizes. #120387

Are you sure you want to change the base?

[X86] Add atomic vector tests for unaligned >1 sizes. #120387

Uh oh!

Conversation

jofrn commented Dec 18, 2024 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

llvmbot commented Dec 18, 2024

Uh oh!

RKSimon Dec 18, 2024

Choose a reason for hiding this comment

Uh oh!

RKSimon left a comment

Choose a reason for hiding this comment

Uh oh!

jyknight commented Dec 18, 2024

Uh oh!

arsenm Dec 19, 2024

Choose a reason for hiding this comment

Uh oh!

jofrn Dec 20, 2024

Choose a reason for hiding this comment

Uh oh!

arsenm Jan 6, 2025

Choose a reason for hiding this comment

Uh oh!

Uh oh!

arsenm Dec 19, 2024

Choose a reason for hiding this comment

Uh oh!

jofrn Dec 20, 2024

Choose a reason for hiding this comment

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

5 participants

jofrn commented Dec 18, 2024 •

edited

Loading