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[AMDGPU] Add tests for v_sat_pk_u8_i16 codegen #122438

Merged
merged 4 commits into from
Jan 15, 2025
Merged

[AMDGPU] Add tests for v_sat_pk_u8_i16 codegen #122438

merged 4 commits into from
Jan 15, 2025

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Shoreshen
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@Shoreshen Shoreshen commented Jan 10, 2025 •
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Preparation for #121124

This PR provides tests added into PR that add selection patterns for instruction v_sat_pk, in order to specify the change of the tests before and after the commit.

Pre-commit tests PR for #121124 : Add selection patterns for instruction v_sat_pk

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llvmbot commented Jan 10, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: None (Shoreshen)

Changes

Patch is 42.56 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/122438.diff

1 Files Affected:

  • (modified) llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll (+803-2)
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index b919bf0605a121..9d2803152974e1 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -2,10 +2,12 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=SDAG-VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=SDAG-GFX9 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1101 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,SDAG-GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=SDAG-GFX12 %s
 
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -global-isel < %s | FileCheck -check-prefixes=GISEL-VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -global-isel < %s | FileCheck -check-prefixes=GISEL-GFX9 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1101 -verify-machineinstrs -global-isel < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -global-isel < %s | FileCheck -check-prefixes=GISEL-GFX12 %s
 
 ; <GFX9 has no V_SAT_PK, GFX9+ has V_SAT_PK, GFX11 has V_SAT_PK with t16
 
@@ -46,6 +48,19 @@ define <2 x i16> @basic_smax_smin(i16 %src0, i16 %src1) {
 ; SDAG-GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
 ; SDAG-GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
+; SDAG-GFX12-LABEL: basic_smax_smin:
+; SDAG-GFX12:       ; %bb.0:
+; SDAG-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_expcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_samplecnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT:    v_med3_i16 v0, v0, 0, 0xff
+; SDAG-GFX12-NEXT:    v_med3_i16 v1, v1, 0, 0xff
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; SDAG-GFX12-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GISEL-VI-LABEL: basic_smax_smin:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -76,6 +91,21 @@ define <2 x i16> @basic_smax_smin(i16 %src0, i16 %src1) {
 ; GISEL-GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; GISEL-GFX11-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GISEL-GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GISEL-GFX12-LABEL: basic_smax_smin:
+; GISEL-GFX12:       ; %bb.0:
+; GISEL-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_expcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_samplecnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_kmcnt 0x0
+; GISEL-GFX12-NEXT:    v_med3_i16 v0, v0, 0, 0xff
+; GISEL-GFX12-NEXT:    v_med3_i16 v1, v1, 0, 0xff
+; GISEL-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-GFX12-NEXT:    s_setpc_b64 s[30:31]
+
   %src0.max = call i16 @llvm.smax.i16(i16 %src0, i16 0)
   %src0.clamp = call i16 @llvm.smin.i16(i16 %src0.max, i16 255)
   %src1.max = call i16 @llvm.smax.i16(i16 %src1, i16 0)
@@ -128,6 +158,19 @@ define amdgpu_kernel void @basic_smax_smin_sgpr(ptr addrspace(1) %out, i32 inreg
 ; SDAG-GFX11-NEXT:    global_store_b32 v2, v0, s[0:1]
 ; SDAG-GFX11-NEXT:    s_endpgm
 ;
+; SDAG-GFX12-LABEL: basic_smax_smin_sgpr:
+; SDAG-GFX12:       ; %bb.0:
+; SDAG-GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; SDAG-GFX12-NEXT:    v_mov_b32_e32 v2, 0
+; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT:    v_med3_i16 v0, s2, 0, 0xff
+; SDAG-GFX12-NEXT:    v_med3_i16 v1, s3, 0, 0xff
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; SDAG-GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX12-NEXT:    global_store_b32 v2, v0, s[0:1]
+; SDAG-GFX12-NEXT:    s_endpgm
+;
 ; GISEL-VI-LABEL: basic_smax_smin_sgpr:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
@@ -192,6 +235,28 @@ define amdgpu_kernel void @basic_smax_smin_sgpr(ptr addrspace(1) %out, i32 inreg
 ; GISEL-GFX11-NEXT:    v_mov_b32_e32 v0, s2
 ; GISEL-GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GISEL-GFX11-NEXT:    s_endpgm
+;
+; GISEL-GFX12-LABEL: basic_smax_smin_sgpr:
+; GISEL-GFX12:       ; %bb.0:
+; GISEL-GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s4, 0
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s5, 0xff
+; GISEL-GFX12-NEXT:    v_mov_b32_e32 v1, 0
+; GISEL-GFX12-NEXT:    s_wait_kmcnt 0x0
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s2, s2
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s3, s3
+; GISEL-GFX12-NEXT:    s_max_i32 s2, s2, s4
+; GISEL-GFX12-NEXT:    s_max_i32 s3, s3, s4
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s2, s2
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s3, s3
+; GISEL-GFX12-NEXT:    s_min_i32 s2, s2, s5
+; GISEL-GFX12-NEXT:    s_min_i32 s3, s3, s5
+; GISEL-GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GISEL-GFX12-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GISEL-GFX12-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX12-NEXT:    s_endpgm
+
   %src0 = trunc i32 %src0ext to i16
   %src1 = trunc i32 %src1ext to i16
   %src0.max = call i16 @llvm.smax.i16(i16 %src0, i16 0)
@@ -235,6 +300,19 @@ define <2 x i16> @basic_smin_smax(i16 %src0, i16 %src1) {
 ; SDAG-GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
 ; SDAG-GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
+; SDAG-GFX12-LABEL: basic_smin_smax:
+; SDAG-GFX12:       ; %bb.0:
+; SDAG-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_expcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_samplecnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT:    v_med3_i16 v0, v0, 0, 0xff
+; SDAG-GFX12-NEXT:    v_med3_i16 v1, v1, 0, 0xff
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; SDAG-GFX12-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GISEL-VI-LABEL: basic_smin_smax:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -265,6 +343,21 @@ define <2 x i16> @basic_smin_smax(i16 %src0, i16 %src1) {
 ; GISEL-GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; GISEL-GFX11-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GISEL-GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GISEL-GFX12-LABEL: basic_smin_smax:
+; GISEL-GFX12:       ; %bb.0:
+; GISEL-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_expcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_samplecnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_kmcnt 0x0
+; GISEL-GFX12-NEXT:    v_med3_i16 v0, v0, 0, 0xff
+; GISEL-GFX12-NEXT:    v_med3_i16 v1, v1, 0, 0xff
+; GISEL-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-GFX12-NEXT:    s_setpc_b64 s[30:31]
+
   %src0.min = call i16 @llvm.smin.i16(i16 %src0, i16 255)
   %src0.clamp = call i16 @llvm.smax.i16(i16 %src0.min, i16 0)
   %src1.min = call i16 @llvm.smin.i16(i16 %src1, i16 255)
@@ -305,6 +398,19 @@ define <2 x i16> @basic_smin_smax_combined(i16 %src0, i16 %src1) {
 ; SDAG-GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
 ; SDAG-GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
+; SDAG-GFX12-LABEL: basic_smin_smax_combined:
+; SDAG-GFX12:       ; %bb.0:
+; SDAG-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_expcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_samplecnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT:    v_med3_i16 v0, v0, 0, 0xff
+; SDAG-GFX12-NEXT:    v_med3_i16 v1, v1, 0, 0xff
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; SDAG-GFX12-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GISEL-VI-LABEL: basic_smin_smax_combined:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -335,6 +441,21 @@ define <2 x i16> @basic_smin_smax_combined(i16 %src0, i16 %src1) {
 ; GISEL-GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; GISEL-GFX11-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GISEL-GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GISEL-GFX12-LABEL: basic_smin_smax_combined:
+; GISEL-GFX12:       ; %bb.0:
+; GISEL-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_expcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_samplecnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_kmcnt 0x0
+; GISEL-GFX12-NEXT:    v_med3_i16 v0, v0, 0, 0xff
+; GISEL-GFX12-NEXT:    v_med3_i16 v1, v1, 0, 0xff
+; GISEL-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX12-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-GFX12-NEXT:    s_setpc_b64 s[30:31]
+
   %src0.min = call i16 @llvm.smin.i16(i16 %src0, i16 255)
   %src0.clamp = call i16 @llvm.smax.i16(i16 %src0.min, i16 0)
   %src1.max = call i16 @llvm.smax.i16(i16 %src1, i16 0)
@@ -373,6 +494,18 @@ define <2 x i16> @vec_smax_smin(<2 x i16> %src) {
 ; SDAG-GFX11-NEXT:    v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
 ; SDAG-GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
+; SDAG-GFX12-LABEL: vec_smax_smin:
+; SDAG-GFX12:       ; %bb.0:
+; SDAG-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_expcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_samplecnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT:    v_pk_max_i16 v0, v0, 0
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX12-NEXT:    v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
+; SDAG-GFX12-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GISEL-VI-LABEL: vec_smax_smin:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -400,6 +533,19 @@ define <2 x i16> @vec_smax_smin(<2 x i16> %src) {
 ; GISEL-GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GISEL-GFX11-NEXT:    v_pk_min_i16 v0, 0xff00ff, v0
 ; GISEL-GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GISEL-GFX12-LABEL: vec_smax_smin:
+; GISEL-GFX12:       ; %bb.0:
+; GISEL-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_expcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_samplecnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_kmcnt 0x0
+; GISEL-GFX12-NEXT:    v_pk_max_i16 v0, v0, 0
+; GISEL-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX12-NEXT:    v_pk_min_i16 v0, 0xff00ff, v0
+; GISEL-GFX12-NEXT:    s_setpc_b64 s[30:31]
+
   %src.max = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %src, <2 x i16> <i16 0, i16 0>)
   %src.clamp = call <2 x i16> @llvm.smin.v2i16(<2 x i16> %src.max, <2 x i16> <i16 255, i16 255>)
   ret <2 x i16> %src.clamp
@@ -449,6 +595,17 @@ define amdgpu_kernel void @vec_smax_smin_sgpr(ptr addrspace(1) %out, <2 x i16> i
 ; SDAG-GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; SDAG-GFX11-NEXT:    s_endpgm
 ;
+; SDAG-GFX12-LABEL: vec_smax_smin_sgpr:
+; SDAG-GFX12:       ; %bb.0:
+; SDAG-GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
+; SDAG-GFX12-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT:    v_pk_max_i16 v0, s2, 0
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX12-NEXT:    v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
+; SDAG-GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]
+; SDAG-GFX12-NEXT:    s_endpgm
+;
 ; GISEL-VI-LABEL: vec_smax_smin_sgpr:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_load_dword s2, s[4:5], 0x2c
@@ -521,6 +678,30 @@ define amdgpu_kernel void @vec_smax_smin_sgpr(ptr addrspace(1) %out, <2 x i16> i
 ; GISEL-GFX11-NEXT:    v_mov_b32_e32 v0, s2
 ; GISEL-GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GISEL-GFX11-NEXT:    s_endpgm
+;
+; GISEL-GFX12-LABEL: vec_smax_smin_sgpr:
+; GISEL-GFX12:       ; %bb.0:
+; GISEL-GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s3, 0
+; GISEL-GFX12-NEXT:    v_mov_b32_e32 v1, 0
+; GISEL-GFX12-NEXT:    s_wait_kmcnt 0x0
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s4, s2
+; GISEL-GFX12-NEXT:    s_ashr_i32 s2, s2, 16
+; GISEL-GFX12-NEXT:    s_max_i32 s3, s4, s3
+; GISEL-GFX12-NEXT:    s_max_i32 s2, s2, 0
+; GISEL-GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-GFX12-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s3, 0xff00ff
+; GISEL-GFX12-NEXT:    s_sext_i32_i16 s4, s2
+; GISEL-GFX12-NEXT:    s_ashr_i32 s2, s2, 16
+; GISEL-GFX12-NEXT:    s_min_i32 s3, s4, s3
+; GISEL-GFX12-NEXT:    s_min_i32 s2, s2, 0xff
+; GISEL-GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GISEL-GFX12-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GISEL-GFX12-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GISEL-GFX12-NEXT:    s_endpgm
+
   %src.max = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %src, <2 x i16> <i16 0, i16 0>)
   %src.clamp = call <2 x i16> @llvm.smin.v2i16(<2 x i16> %src.max, <2 x i16> <i16 255, i16 255>)
   store <2 x i16> %src.clamp, ptr addrspace(1) %out
@@ -556,6 +737,18 @@ define <2 x i16> @vec_smin_smax(<2 x i16> %src) {
 ; SDAG-GFX11-NEXT:    v_pk_max_i16 v0, v0, 0
 ; SDAG-GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
+; SDAG-GFX12-LABEL: vec_smin_smax:
+; SDAG-GFX12:       ; %bb.0:
+; SDAG-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_expcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_samplecnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT:    v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX12-NEXT:    v_pk_max_i16 v0, v0, 0
+; SDAG-GFX12-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GISEL-VI-LABEL: vec_smin_smax:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -583,9 +776,617 @@ define <2 x i16> @vec_smin_smax(<2 x i16> %src) {
 ; GISEL-GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GISEL-GFX11-NEXT:    v_pk_max_i16 v0, v0, 0
 ; GISEL-GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GISEL-GFX12-LABEL: vec_smin_smax:
+; GISEL-GFX12:       ; %bb.0:
+; GISEL-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_expcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_samplecnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_kmcnt 0x0
+; GISEL-GFX12-NEXT:    v_pk_min_i16 v0, 0xff00ff, v0
+; GISEL-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX12-NEXT:    v_pk_max_i16 v0, v0, 0
+; GISEL-GFX12-NEXT:    s_setpc_b64 s[30:31]
+
   %src.min = call <2 x i16> @llvm.smin.v2i16(<2 x i16> %src, <2 x i16> <i16 255, i16 255>)
   %src.clamp = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %src.min, <2 x i16> <i16 0, i16 0>)
   ret <2 x i16> %src.clamp
 }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11: {{.*}}
+define i16 @basic_smax_smin_bit_or(i16 %src0, i16 %src1) {
+; SDAG-VI-LABEL: basic_smax_smin_bit_or:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT:    v_max_i16_e32 v0, 0, v0
+; SDAG-VI-NEXT:    v_max_i16_e32 v1, 0, v1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, 0xff
+; SDAG-VI-NEXT:    v_min_i16_e32 v0, 0xff, v0
+; SDAG-VI-NEXT:    v_min_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-VI-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG-VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9-LABEL: basic_smax_smin_bit_or:
+; SDAG-GFX9:       ; %bb.0:
+; SDAG-GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9-NEXT:    v_mov_b32_e32 v2, 0xff
+; SDAG-GFX9-NEXT:    v_med3_i16 v1, v1, 0, v2
+; SDAG-GFX9-NEXT:    v_med3_i16 v0, v0, 0, v2
+; SDAG-GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
+; SDAG-GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG-GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: basic_smax_smin_bit_or:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_med3_i16 v1, v1, 0, 0xff
+; GFX11-NEXT:    v_med3_i16 v0, v0, 0, 0xff
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG-GFX12-LABEL: basic_smax_smin_bit_or:
+; SDAG-GFX12:       ; %bb.0:
+; SDAG-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_expcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_samplecnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; SDAG-GFX12-NEXT:    s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT:    v_med3_i16 v1, v1, 0, 0xff
+; SDAG-GFX12-NEXT:    v_med3_i16 v0, v0, 0, 0xff
+; SDAG-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX12-NEXT:    v_lshlrev_b16 v1, 8, v1
+; SDAG-GFX12-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG-GFX12-NEXT:    s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: basic_smax_smin_bit_or:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT:    v_max_i16_e32 v0, 0, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, 0xff
+; GISEL-VI-NEXT:    v_max_i16_e32 v1, 0, v1
+; GISEL-VI-NEXT:    v_min_i16_e32 v0, 0xff, v0
+; GISEL-VI-NEXT:    v_min_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GISEL-VI-NEXT:    v_or_b32_e32 v0, v0, v1
+; GISEL-VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9-LABEL: basic_smax_smin_bit_or:
+; GISEL-GFX9:       ; %bb.0:
+; GISEL-GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9-NEXT:    v_mov_b32_e32 v2, 0xff
+; GISEL-GFX9-NEXT:    v_med3_i16 v1, v1, 0, v2
+; GISEL-GFX9-NEXT:    v_med3_i16 v0, v0, 0, v2
+; GISEL-GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
+; GISEL-GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
+; GISEL-GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GISEL-GFX12-LABEL: basic_smax_smin_bit_or:
+; GISEL-GFX12:       ; %bb.0:
+; GISEL-GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_expcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_samplecnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_bvhcnt 0x0
+; GISEL-GFX12-NEXT:    s_wait_kmcnt 0x0
+; GISEL-GFX12-NEXT:    v_med3_i16 v1, v1, 0, 0xff
+; GISEL-GFX12-NEXT:    v_med3_i16 v0, v0, 0, 0xff
+; GISEL-GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX12-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GISEL-GFX12-NEXT:    v_or_b32_e32 v0, v0, v1
+; GISEL-GFX12-NEXT:    s_setpc_b64 s[30:31]
+
+  %src0.max = call i16 @llvm.smax.i16(i16 %src0, i16 0)
+  %src0.clamp = call i16 @llvm.smin.i16(i16 %src0.max, i16 255)
+  %src1.max = call i16 @llvm.smax.i16(i16 %src1, i16 0)
+  %src1.clamp = call i16 @llvm.smin.i16(i16 %src1.max, i16 255)
+  %src0.and = and i16 %src0.clamp, 255
+  %src1.shl = shl i16 %src1.clamp, 8
+  %or = or i16 %src0.and, %src1.shl
+  ret i16 %or
+}
+define i16 @basic_umax_umin_bit_or(i16 %src0, i16 %src1) {
+; SDAG-VI-LABEL: basic_umax_umin_bit_or:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, 0xff
+; SDAG-VI-NEXT:    v_min_u16_e32 v0, 0xff, v0
+; SDAG-VI-NEXT:    v_min_u16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-VI-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG-VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9-LABEL: basic_umax_umin_bit_or:
+; SDAG-GFX9:       ; %bb.0:
+; SDAG-GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9-NEXT:    s_movk_i32 s4, 0xff
+; SDAG-GFX9-NEXT:    v_min_u16_e32 v0, 0xff, v0
+; SDAG-GFX9-NEXT:    v_min_u16_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG-GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: basic_umax_umin_bit_or:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_min_u16 v1, 0xff, v1
+; GFX11-NEXT:    v_min_u16 v0, 0xff, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:...
[truncated]

@Shoreshen Shoreshen changed the title precommit-tests-#121124 [AMDGPU]precommit-tests-#121124 Jan 10, 2025
@Shoreshen Shoreshen closed this Jan 10, 2025
@Shoreshen Shoreshen reopened this Jan 10, 2025
@Pierre-vh Pierre-vh self-requested a review January 10, 2025 11:57
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⚠️ undef deprecator found issues in your code. ⚠️

You can test this locally with the following command: 
git diff -U0 --pickaxe-regex -S '([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)' 46ca6dfb5f0783d68cd738501a26a1a9455ff74e dd38801174f9e8562f7d48bd52cb5001a5377197 llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll

The following files introduce new uses of undef:

  • llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll

Undef is now deprecated and should only be used in the rare cases where no replacement is possible. For example, a load of uninitialized memory yields undef. You should use poison values for placeholders instead.

In tests, avoid using undef and having tests that trigger undefined behavior. If you need an operand with some unimportant value, you can add a new argument to the function and use that instead.

For example, this is considered a bad practice:

define void @fn() {
  ...
  br i1 undef, ...
}

Please use the following instead:

define void @fn(i1 %cond) {
  ...
  br i1 %cond, ...
}

Please refer to the Undefined Behavior Manual for more information.

@Shoreshen Shoreshen changed the title [AMDGPU]precommit-tests-#121124 [AMDGPU] precommit tests #121124 Jan 10, 2025
arsenm
arsenm reviewed Jan 10, 2025
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Description should say what the tests are for

@Shoreshen
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Description should say what the tests are for

Thanks, added~~

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arsenm commented Jan 13, 2025

Description should say what the tests are for

Thanks, added~~

The title is still not useful, the first line should have a real description

@Shoreshen
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Description should say what the tests are for

Thanks, added~~

The title is still not useful, the first line should have a real description

Hi @arsenm , could you be more specific about real description??

I do not have previous experience about it, what kind of information or format would be preferred

Thanks

@Shoreshen Shoreshen requested a review from arsenm January 13, 2025 04:41
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arsenm commented Jan 13, 2025

Hi @arsenm , could you be more specific about real description??

"precommit tests #121124" is a random number with no meaning. The link to the PR is secondary to the description. Should be approximately swapped with what you have

@Shoreshen
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Hi @arsenm , could you be more specific about real description??

"precommit tests #121124" is a random number with no meaning. The link to the PR is secondary to the description. Should be approximately swapped with what you have

Hi @arsenm , so in the first line what if I do the following:

  1. Indicating that this PR is to provides tests to other PR
  2. The functionality of the PR that it provided to
  3. The purpose of providing test

would that be OK??

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You can do the following I think:

[AMDGPU] Add tests for v_sat_pk_u8_i16 codegen

Preparation for #121124

@Shoreshen Shoreshen changed the title [AMDGPU] precommit tests #121124 [AMDGPU] Add tests for v_sat_pk_u8_i16 codegen Jan 14, 2025
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Hi if all things looks fine, can some submit it for me, I don't have access. Thanks

@kzhuravl kzhuravl merged commit b665ddd into llvm:main Jan 15, 2025
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@Shoreshen Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.

Please check whether problems have been caused by your change specifically, as the builds can include changes from many authors. It is not uncommon for your change to be included in a build that fails due to someone else's changes, or infrastructure issues.

How to do this, and the rest of the post-merge process, is covered in detail here.

If your change does cause a problem, it may be reverted, or you can revert it yourself. This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again.

If you don't get any reports, no action is required from you. Your changes are working as expected, well done!

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llvm-ci commented Jan 15, 2025

LLVM Buildbot has detected a new failure on builder openmp-offload-libc-amdgpu-runtime running on omp-vega20-1 while building llvm at step 7 "Add check check-offload".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/11721

Here is the relevant piece of the build log for the reference 
Step 7 (Add check check-offload) failure: test (failure)
******************** TEST 'libomptarget :: amdgcn-amd-amdhsa :: offloading/pgo1.c' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 1
/home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./bin/clang -fopenmp    -I /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.src/offload/test -I /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src -L /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload -L /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./lib -L /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src  -nogpulib -Wl,-rpath,/home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload -Wl,-rpath,/home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src -Wl,-rpath,/home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./lib  -fopenmp-targets=amdgcn-amd-amdhsa /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c -o /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/pgo1.c.tmp -Xoffload-linker -lc -Xoffload-linker -lm /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./lib/libomptarget.devicertl.a -fprofile-instr-generate      -Xclang "-fprofile-instrument=clang"
# executed command: /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./bin/clang -fopenmp -I /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.src/offload/test -I /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src -L /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload -L /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./lib -L /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src -nogpulib -Wl,-rpath,/home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload -Wl,-rpath,/home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src -Wl,-rpath,/home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./lib -fopenmp-targets=amdgcn-amd-amdhsa /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c -o /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/pgo1.c.tmp -Xoffload-linker -lc -Xoffload-linker -lm /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./lib/libomptarget.devicertl.a -fprofile-instr-generate -Xclang -fprofile-instrument=clang
# RUN: at line 3
/home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/pgo1.c.tmp 2>&1 | /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./bin/FileCheck /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c      --check-prefix="CLANG-PGO"
# executed command: /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/pgo1.c.tmp
# executed command: /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.build/./bin/FileCheck /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c --check-prefix=CLANG-PGO
# .---command stderr------------
# | /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c:32:20: error: CLANG-PGO-NEXT: expected string not found in input
# | // CLANG-PGO-NEXT: [ 0 11 20 ]
# |                    ^
# | <stdin>:3:28: note: scanning from here
# | ======== Counters =========
# |                            ^
# | <stdin>:4:1: note: possible intended match here
# | [ 0 13 20 ]
# | ^
# | 
# | Input file: <stdin>
# | Check file: /home/ompworker/bbot/openmp-offload-libc-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# |            1: ======= GPU Profile ======= 
# |            2: Target: amdgcn-amd-amdhsa 
# |            3: ======== Counters ========= 
# | next:32'0                                X error: no match found
# |            4: [ 0 13 20 ] 
# | next:32'0     ~~~~~~~~~~~~
# | next:32'1     ?            possible intended match
# |            5: [ 10 ] 
# | next:32'0     ~~~~~~~
# |            6: [ 20 ] 
# | next:32'0     ~~~~~~~
# |            7: ========== Data =========== 
# | next:32'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# |            8: { 9515997471539760012 4749112401 0xffffffffffffffd8 0x0 0x0 0x0 3 [...] 0 } 
# | next:32'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# |            9: { 3666282617048535130 24 0xffffffffffffffb0 0x0 0x0 0x0 1 [...] 0 } 
# | next:32'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# |            .
# |            .
# |            .
...

paulhuggett pushed a commit to paulhuggett/llvm-project that referenced this pull request Jan 16, 2025
@Shoreshen @paulhuggett
[AMDGPU] Add tests for v_sat_pk_u8_i16 codegen (llvm#122438)
7f969a9 
Preparation for llvm#121124 

This PR provides tests added into
[PR](llvm#121124) that add
selection patterns for instruction `v_sat_pk`, in order to specify the
change of the tests before and after the commit.

Pre-commit tests PR for llvm#121124 : Add selection patterns for instruction
`v_sat_pk`
DKLoehr pushed a commit to DKLoehr/llvm-project that referenced this pull request Jan 17, 2025
@Shoreshen @DKLoehr
[AMDGPU] Add tests for v_sat_pk_u8_i16 codegen (llvm#122438)
37aef22 
Preparation for llvm#121124 

This PR provides tests added into
[PR](llvm#121124) that add
selection patterns for instruction `v_sat_pk`, in order to specify the
change of the tests before and after the commit.

Pre-commit tests PR for llvm#121124 : Add selection patterns for instruction
`v_sat_pk`
@Shoreshen Shoreshen deleted the precommit-tests-121124 branch January 22, 2025 07:49
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@shiltian shiltian shiltian approved these changes

@Pierre-vh Pierre-vh Awaiting requested review from Pierre-vh

@arsenm arsenm Awaiting requested review from arsenm

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