[RISCV] Add riscv_atomic.h and Zawrs builtins

[wangpc-pp]

riscv_atomic.h contains all builtins for atomics.

Currently, we suppoprt builtins for Zawrs extension.

Doc: riscv-non-isa/riscv-c-api-doc#79

[llvmbot]

@llvm/pr-subscribers-clang-codegen
@llvm/pr-subscribers-backend-x86
@llvm/pr-subscribers-llvm-ir
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang

Author: Pengcheng Wang (wangpc-pp)

Changes

riscv_atomic.h contains all builtins for atomics.

Currently, we suppoprt builtins for Zawrs extension.

Doc: riscv-non-isa/riscv-c-api-doc#79

---

Full diff: https://github.com/llvm/llvm-project/pull/96283.diff

8 Files Affected:

• (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+8)
• (modified) clang/lib/CodeGen/CGBuiltin.cpp (+8)
• (modified) clang/lib/Headers/CMakeLists.txt (+1)
• (added) clang/lib/Headers/riscv_atomic.h (+18)
• (added) clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c (+42)
• (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+10)
• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZa.td (+4-1)
• (added) llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll (+33)

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..429f1356aa5fd 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,11 @@ let Features = "zihintntl", Attributes = [CustomTypeChecking] in {
 def ntl_load : RISCVBuiltin<"void(...)">;
 def ntl_store : RISCVBuiltin<"void(...)">;
 } // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===----------------------------------------------------------------------===//
+// Zawrs extension.
+//===----------------------------------------------------------------------===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2516ed4508242..1e130cad6d00d 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21834,6 +21834,14 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
     ID = Intrinsic::riscv_sm3p1;
     break;
 
+  // Zawrs
+  case RISCV::BI__builtin_riscv_wrs_nto:
+    ID = Intrinsic::riscv_wrs_nto;
+    break;
+  case RISCV::BI__builtin_riscv_wrs_sto:
+    ID = Intrinsic::riscv_wrs_sto;
+    break;
+
   // Zihintntl
   case RISCV::BI__builtin_riscv_ntl_load: {
     llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 89fa0ecd45eb4..f8f430e6921cb 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
   )
 
 set(riscv_files
+  riscv_atomic.h
   riscv_bitmanip.h
   riscv_crypto.h
   riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomic.h b/clang/lib/Headers/riscv_atomic.h
new file mode 100644
index 0000000000000..4c548bdfa8253
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomic.h
@@ -0,0 +1,18 @@
+/*===---- riscv_atomic.h - RISC-V atomic intrinsics ------------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __RISCV_ATOMIC_H
+#define __RISCV_ATOMIC_H
+
+#ifdef __riscv_zawrs
+#define __riscv_wrs_nto __builtin_riscv_wrs_nto
+#define __riscv_wrs_sto __builtin_riscv_wrs_sto
+#endif
+
+#endif
diff --git a/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
new file mode 100644
index 0000000000000..e3d4899244ca4
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zawrs -disable-O0-optnone \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefixes=CHECK-RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zawrs -disable-O0-optnone \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_atomic.h>
+
+// CHECK-RV32-LABEL: define dso_local void @zawrs_nto
+// CHECK-RV32-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    call void @llvm.riscv.wrs.nto()
+// CHECK-RV32-NEXT:    ret void
+//
+// CHECK-RV64-LABEL: define dso_local void @zawrs_nto
+// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    call void @llvm.riscv.wrs.nto()
+// CHECK-RV64-NEXT:    ret void
+//
+void zawrs_nto() {
+  __riscv_wrs_nto();
+}
+
+// CHECK-RV32-LABEL: define dso_local void @zawrs_sto
+// CHECK-RV32-SAME: () #[[ATTR0]] {
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    call void @llvm.riscv.wrs.sto()
+// CHECK-RV32-NEXT:    ret void
+//
+// CHECK-RV64-LABEL: define dso_local void @zawrs_sto
+// CHECK-RV64-SAME: () #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    call void @llvm.riscv.wrs.sto()
+// CHECK-RV64-NEXT:    ret void
+//
+void zawrs_sto() {
+  __riscv_wrs_sto();
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 2da154c300344..cd5740fa2d3ac 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -124,6 +124,16 @@ let TargetPrefix = "riscv" in {
                               [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
 } // TargetPrefix = "riscv"
 
+//===----------------------------------------------------------------------===//
+// 'Zawrs' (Wait on Reservation Set)
+
+let TargetPrefix = "riscv" in {
+  def int_riscv_wrs_nto
+      : DefaultAttrsIntrinsic<[], [], [IntrHasSideEffects]>;
+  def int_riscv_wrs_sto
+      : DefaultAttrsIntrinsic<[], [], [IntrHasSideEffects]>;
+} // TargetPrefix = "riscv"
+
 //===----------------------------------------------------------------------===//
 // Vectors
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
index 1ee78359bc4a5..cdf60dae0574f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
@@ -123,7 +123,7 @@ defm : AMOCASPat<"atomic_cmp_swap_i64", "AMOCAS_D_RV64", i64, [IsRV64]>;
 // Zawrs (Wait-on-Reservation-Set)
 //===----------------------------------------------------------------------===//
 
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
 class WRSInst<bits<12> funct12, string opcodestr>
     : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), opcodestr, ""> {
   let rs1 = 0;
@@ -134,6 +134,9 @@ class WRSInst<bits<12> funct12, string opcodestr>
 let Predicates = [HasStdExtZawrs] in {
 def WRS_NTO : WRSInst<0b000000001101, "wrs.nto">, Sched<[]>;
 def WRS_STO : WRSInst<0b000000011101, "wrs.sto">, Sched<[]>;
+
+def : Pat<(int_riscv_wrs_nto), (WRS_NTO)>;
+def : Pat<(int_riscv_wrs_sto), (WRS_NTO)>;
 } // Predicates = [HasStdExtZawrs]
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll b/llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll
new file mode 100644
index 0000000000000..fa45f049ea818
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zawrs-intrinsic.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zawrs -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+zawrs -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64
+
+define void @wrs_nto() {
+; RV32-LABEL: wrs_nto:
+; RV32:       # %bb.0:
+; RV32-NEXT:    wrs.nto
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: wrs_nto:
+; RV64:       # %bb.0:
+; RV64-NEXT:    wrs.nto
+; RV64-NEXT:    ret
+  call void @llvm.riscv.wrs.nto()
+  ret void
+}
+
+define void @wrs_sto() {
+; RV32-LABEL: wrs_sto:
+; RV32:       # %bb.0:
+; RV32-NEXT:    wrs.nto
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: wrs_sto:
+; RV64:       # %bb.0:
+; RV64-NEXT:    wrs.nto
+; RV64-NEXT:    ret
+  call void @llvm.riscv.wrs.sto()
+  ret void
+}