fix typo

loongson · Apr 20, 2023 · f05f844 · f05f844
1 parent 55dbaad
commit f05f844
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diff --git a/...ns/overview-of-basic-integer-instructions/other-miscellaneous-instructions.adoc b/...ns/overview-of-basic-integer-instructions/other-miscellaneous-instructions.adoc
@@ -325,7 +325,7 @@ That is, information such as "`Loongson3A5000 @ 2.5GHz`"
 |`1` indicates that the Cache shown by `L1 IU_Present` is the unified Cache
 
 ^m|2
-^m|L1 D Prwsent
+^m|L1 D Present
 |`1` indicates there is a first-level data Cache
 
 ^m|3
@@ -377,7 +377,7 @@ That is, information such as "`Loongson3A5000 @ 2.5GHz`"
 |`1` indicates there is a three-level data Cache
 
 ^m|15
-^m|L3 F Inclusive
+^m|L3 D Private
 |`1` indicates that the three-level data Cache is private to each core
 
 ^m|16

diff --git a/...ual-EN/la464-processor-core/instruction-set-features-implemented-in-3a5000.adoc b/...ual-EN/la464-processor-core/instruction-set-features-implemented-in-3a5000.adoc
@@ -252,7 +252,7 @@ m|L1 IU Unify
 m|1'b0
 
 ^m|2
-m|L1 D Prwsent
+m|L1 D Present
 |`1` indicates there is a first-level data Cache
 m|1'b1
 
@@ -317,7 +317,7 @@ m|L3 D Present
 m|1'b0
 
 ^m|15
-m|L3 F Inclusive
+m|L3 D Private
 |`1` indicates that the three-level data Cache is private to each core
 m|1'b0