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Update (2024.01.26, 3rd)
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24527: Fix a typo for invokeinterface in #8604
29494: Fix assert(_succ != current) failed: invariant
32874: Amend 30985: Insert acqure membar for load-exclusive with acquire to fix typo
29823: Fix ShenandoahGC cmpxchg_oop register be clobbered issue
32796: Rethinking the ties-to-positive round mode
32688: Revamp the SIMD string compress routines
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@loongson-jvm
loongson-jvm authored Jan 26, 2024
1 parent 3cd251b commit 797f2a2
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Showing 11 changed files with 446 additions and 135 deletions.
63 changes: 62 additions & 1 deletion src/hotspot/cpu/loongarch/assembler_loongarch.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -970,6 +970,10 @@ class Assembler : public AbstractAssembler {
vshuf_h_op = 0b01110001011110101,
vshuf_w_op = 0b01110001011110110,
vshuf_d_op = 0b01110001011110111,
vslti_b_op = 0b01110010100001100,
vslti_h_op = 0b01110010100001101,
vslti_w_op = 0b01110010100001110,
vslti_d_op = 0b01110010100001111,
vslti_bu_op = 0b01110010100010000,
vslti_hu_op = 0b01110010100010001,
vslti_wu_op = 0b01110010100010010,
Expand Down Expand Up @@ -1146,6 +1150,10 @@ class Assembler : public AbstractAssembler {
xvshuf_w_op = 0b01110101011110110,
xvshuf_d_op = 0b01110101011110111,
xvperm_w_op = 0b01110101011111010,
xvslti_b_op = 0b01110110100001100,
xvslti_h_op = 0b01110110100001101,
xvslti_w_op = 0b01110110100001110,
xvslti_d_op = 0b01110110100001111,
xvslti_bu_op = 0b01110110100010000,
xvslti_hu_op = 0b01110110100010001,
xvslti_wu_op = 0b01110110100010010,
Expand Down Expand Up @@ -1237,6 +1245,14 @@ class Assembler : public AbstractAssembler {
unknow_ops14 = 0b11111111111111
};

// 13-bit opcode, highest 13 bits: bits[31...19]
enum ops13 {
vldrepl_d_op = 0b0011000000010,
xvldrepl_d_op = 0b0011001000010,

unknow_ops13 = 0b1111111111111
};

// 12-bit opcode, highest 12 bits: bits[31...20]
enum ops12 {
fmadd_s_op = 0b000010000001,
Expand Down Expand Up @@ -1274,10 +1290,20 @@ class Assembler : public AbstractAssembler {
xvbitsel_v_op = 0b000011010010,
vshuf_b_op = 0b000011010101,
xvshuf_b_op = 0b000011010110,
vldrepl_w_op = 0b001100000010,
xvldrepl_w_op = 0b001100100010,

unknow_ops12 = 0b111111111111
};

// 11-bit opcode, highest 11 bits: bits[31...21]
enum ops11 {
vldrepl_h_op = 0b00110000010,
xvldrepl_h_op = 0b00110010010,

unknow_ops11 = 0b11111111111
};

// 10-bit opcode, highest 10 bits: bits[31...22]
enum ops10 {
bstr_w_op = 0b0000000001,
Expand Down Expand Up @@ -1313,6 +1339,8 @@ class Assembler : public AbstractAssembler {
xvst_op = 0b0010110011,
ldl_w_op = 0b0010111000,
ldr_w_op = 0b0010111001,
vldrepl_b_op = 0b0011000010,
xvldrepl_b_op = 0b0011001010,

unknow_ops10 = 0b1111111111
};
Expand Down Expand Up @@ -1491,10 +1519,25 @@ class Assembler : public AbstractAssembler {
// | opcode | I8 | rj | rd |
static inline int insn_I8RR (int op, int imm8, int rj, int rd) { /*assert(is_simm(imm8, 8), "not a signed 8-bit int");*/ return (op<<18) | (low(imm8, 8)<<10) | (rj<<5) | rd; }

// 2RI9-type
// 31 19 18 10 9 5 4 0
// | opcode | I9 | rj | vd |
static inline int insn_I9RR(int op, int imm9, int rj, int vd) { return (op<<19) | (low(imm9, 9)<<10) | (rj<<5) | vd; }

// 2RI10-type
// 31 20 19 10 9 5 4 0
// | opcode | I10 | rj | vd |
static inline int insn_I10RR(int op, int imm10, int rj, int vd) { return (op<<20) | (low(imm10, 10)<<10) | (rj<<5) | vd; }

// 2RI11-type
// 31 21 20 10 9 5 4 0
// | opcode | I11 | rj | vd |
static inline int insn_I11RR(int op, int imm11, int rj, int vd) { return (op<<21) | (low(imm11, 11)<<10) | (rj<<5) | vd; }

// 2RI12-type
// 31 22 21 10 9 5 4 0
// | opcode | I12 | rj | rd |
static inline int insn_I12RR(int op, int imm12, int rj, int rd) { /* assert(is_simm(imm12, 12), "not a signed 12-bit int");*/ return (op<<22) | (low(imm12, 12)<<10) | (rj<<5) | rd; }
static inline int insn_I12RR(int op, int imm12, int rj, int rd) { return (op<<22) | (low(imm12, 12)<<10) | (rj<<5) | rd; }

// 2RI14-type
// 31 24 23 10 9 5 4 0
Expand Down Expand Up @@ -2898,6 +2941,15 @@ class Assembler : public AbstractAssembler {
void xvslt_wu(FloatRegister xd, FloatRegister xj, FloatRegister xk) { ASSERT_LASX emit_int32(insn_RRR(xvslt_wu_op, (int)xk->encoding(), (int)xj->encoding(), (int)xd->encoding())); }
void xvslt_du(FloatRegister xd, FloatRegister xj, FloatRegister xk) { ASSERT_LASX emit_int32(insn_RRR(xvslt_du_op, (int)xk->encoding(), (int)xj->encoding(), (int)xd->encoding())); }

void vslti_b(FloatRegister vd, FloatRegister vj, int si5) { ASSERT_LSX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR( vslti_b_op, si5, (int)vj->encoding(), (int)vd->encoding())); }
void vslti_h(FloatRegister vd, FloatRegister vj, int si5) { ASSERT_LSX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR( vslti_h_op, si5, (int)vj->encoding(), (int)vd->encoding())); }
void vslti_w(FloatRegister vd, FloatRegister vj, int si5) { ASSERT_LSX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR( vslti_w_op, si5, (int)vj->encoding(), (int)vd->encoding())); }
void vslti_d(FloatRegister vd, FloatRegister vj, int si5) { ASSERT_LSX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR( vslti_d_op, si5, (int)vj->encoding(), (int)vd->encoding())); }
void xvslti_b(FloatRegister xd, FloatRegister xj, int si5) { ASSERT_LASX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR(xvslti_b_op, si5, (int)xj->encoding(), (int)xd->encoding())); }
void xvslti_h(FloatRegister xd, FloatRegister xj, int si5) { ASSERT_LASX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR(xvslti_h_op, si5, (int)xj->encoding(), (int)xd->encoding())); }
void xvslti_w(FloatRegister xd, FloatRegister xj, int si5) { ASSERT_LASX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR(xvslti_w_op, si5, (int)xj->encoding(), (int)xd->encoding())); }
void xvslti_d(FloatRegister xd, FloatRegister xj, int si5) { ASSERT_LASX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR(xvslti_d_op, si5, (int)xj->encoding(), (int)xd->encoding())); }

void vslti_bu(FloatRegister vd, FloatRegister vj, int ui5) { ASSERT_LSX emit_int32(insn_I5RR( vslti_bu_op, ui5, (int)vj->encoding(), (int)vd->encoding())); }
void vslti_hu(FloatRegister vd, FloatRegister vj, int ui5) { ASSERT_LSX emit_int32(insn_I5RR( vslti_hu_op, ui5, (int)vj->encoding(), (int)vd->encoding())); }
void vslti_wu(FloatRegister vd, FloatRegister vj, int ui5) { ASSERT_LSX emit_int32(insn_I5RR( vslti_wu_op, ui5, (int)vj->encoding(), (int)vd->encoding())); }
Expand Down Expand Up @@ -3136,6 +3188,15 @@ class Assembler : public AbstractAssembler {
void vstx(FloatRegister vd, Register rj, Register rk) { ASSERT_LSX emit_int32(insn_RRR( vstx_op, (int)rk->encoding(), (int)rj->encoding(), (int)vd->encoding())); }
void xvstx(FloatRegister xd, Register rj, Register rk) { ASSERT_LASX emit_int32(insn_RRR(xvstx_op, (int)rk->encoding(), (int)rj->encoding(), (int)xd->encoding())); }

void vldrepl_d(FloatRegister vd, Register rj, int si9) { ASSERT_LSX assert(is_simm(si9, 9), "not a signed 9-bit int"); emit_int32(insn_I9RR( vldrepl_d_op, si9, (int)rj->encoding(), (int)vd->encoding()));}
void vldrepl_w(FloatRegister vd, Register rj, int si10) { ASSERT_LSX assert(is_simm(si10, 10), "not a signed 10-bit int"); emit_int32(insn_I10RR( vldrepl_w_op, si10, (int)rj->encoding(), (int)vd->encoding()));}
void vldrepl_h(FloatRegister vd, Register rj, int si11) { ASSERT_LSX assert(is_simm(si11, 11), "not a signed 11-bit int"); emit_int32(insn_I11RR( vldrepl_h_op, si11, (int)rj->encoding(), (int)vd->encoding()));}
void vldrepl_b(FloatRegister vd, Register rj, int si12) { ASSERT_LSX assert(is_simm(si12, 12), "not a signed 12-bit int"); emit_int32(insn_I12RR( vldrepl_b_op, si12, (int)rj->encoding(), (int)vd->encoding()));}
void xvldrepl_d(FloatRegister xd, Register rj, int si9) { ASSERT_LASX assert(is_simm(si9, 9), "not a signed 9-bit int"); emit_int32(insn_I9RR(xvldrepl_d_op, si9, (int)rj->encoding(), (int)xd->encoding()));}
void xvldrepl_w(FloatRegister xd, Register rj, int si10) { ASSERT_LASX assert(is_simm(si10, 10), "not a signed 10-bit int"); emit_int32(insn_I10RR(xvldrepl_w_op, si10, (int)rj->encoding(), (int)xd->encoding()));}
void xvldrepl_h(FloatRegister xd, Register rj, int si11) { ASSERT_LASX assert(is_simm(si11, 11), "not a signed 11-bit int"); emit_int32(insn_I11RR(xvldrepl_h_op, si11, (int)rj->encoding(), (int)xd->encoding()));}
void xvldrepl_b(FloatRegister xd, Register rj, int si12) { ASSERT_LASX assert(is_simm(si12, 12), "not a signed 12-bit int"); emit_int32(insn_I12RR(xvldrepl_b_op, si12, (int)rj->encoding(), (int)xd->encoding()));}

#undef ASSERT_LSX
#undef ASSERT_LASX

Expand Down
14 changes: 8 additions & 6 deletions src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -475,7 +475,7 @@ void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm,
assert_different_registers(addr.base(), expected, tmp1, tmp2);
assert_different_registers(addr.base(), new_val, tmp1, tmp2);

Label step4, done_succ, done_fail, done;
Label step4, done_succ, done_fail, done, is_null;

// There are two ways to reach this label. Initial entry into the
// cmpxchg_oop code expansion starts at step1 (which is equivalent
Expand Down Expand Up @@ -544,13 +544,15 @@ void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm,
__ move(tmp1, tmp2);

if (is_narrow) {
__ beqz(tmp1, is_null);
// Decode tmp1 in order to resolve its forward pointer
__ decode_heap_oop(tmp1);
}
resolve_forward_pointer(masm, tmp1);
if (is_narrow) {
__ decode_heap_oop_not_null(tmp1);
resolve_forward_pointer_not_null(masm, tmp1);
// Encode tmp1 to compare against expected.
__ encode_heap_oop(tmp1);
__ encode_heap_oop_not_null(tmp1);
__ bind(is_null);
} else {
resolve_forward_pointer(masm, tmp1);
}

// Does forwarded value of fetched from-space pointer match original
Expand Down
28 changes: 14 additions & 14 deletions src/hotspot/cpu/loongarch/gc/shenandoah/shenandoah_loongarch_64.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -29,16 +29,16 @@ source_hpp %{
%}

encode %{
enc_class loongarch_enc_cmpxchg_oop_shenandoah(memory mem, mRegP oldval, mRegP newval, mRegI res) %{
enc_class loongarch_enc_cmpxchg_oop_shenandoah(indirect mem, mRegP oldval, mRegP newval, mRegI res) %{
MacroAssembler _masm(&cbuf);
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ false, /*is_cae*/ false, $res$$Register);
%}

enc_class loongarch_enc_cmpxchg_acq_oop_shenandoah(memory mem, mRegP oldval, mRegP newval, mRegI res) %{
enc_class loongarch_enc_cmpxchg_acq_oop_shenandoah(indirect mem, mRegP oldval, mRegP newval, mRegI res) %{
MacroAssembler _masm(&cbuf);
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ true, /*is_cae*/ false, $res$$Register);
%}
Expand All @@ -64,7 +64,7 @@ instruct compareAndSwapN_shenandoah(mRegI res, indirect mem, mRegN oldval, mRegN
%}

ins_encode %{
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ false, /*is_cae*/ false, $res$$Register);
%}
Expand Down Expand Up @@ -92,7 +92,7 @@ instruct compareAndSwapNAcq_shenandoah(mRegI res, indirect mem, mRegN oldval, mR
%}

ins_encode %{
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ true, /*is_cae*/ false, $res$$Register);
%}
Expand All @@ -108,7 +108,7 @@ instruct compareAndExchangeN_shenandoah(mRegN res, indirect mem, mRegN oldval, m
%}

ins_encode %{
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ false, /*is_cae*/ true, $res$$Register);
%}
Expand All @@ -124,7 +124,7 @@ instruct compareAndExchangeP_shenandoah(mRegP res, indirect mem, mRegP oldval, m
%}

ins_encode %{
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ false, /*is_cae*/ true, $res$$Register);
%}
Expand All @@ -140,7 +140,7 @@ instruct compareAndExchangeNAcq_shenandoah(mRegN res, indirect mem, mRegN oldval
%}

ins_encode %{
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ true, /*is_cae*/ true, $res$$Register);
%}
Expand All @@ -156,7 +156,7 @@ instruct compareAndExchangePAcq_shenandoah(mRegP res, indirect mem, mRegP oldval
%}

ins_encode %{
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ true, /*is_cae*/ true, $res$$Register);
%}
Expand All @@ -172,7 +172,7 @@ instruct weakCompareAndSwapN_shenandoah(mRegI res, indirect mem, mRegN oldval, m
%}
ins_encode %{
// Weak is not currently supported by ShenandoahBarrierSet::cmpxchg_oop
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ false, /*is_cae*/ false, $res$$Register);
%}
Expand All @@ -189,7 +189,7 @@ instruct weakCompareAndSwapP_shenandoah(mRegI res, indirect mem, mRegP oldval, m

ins_encode %{
// Weak is not currently supported by ShenandoahBarrierSet::cmpxchg_oop
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ false, /*is_cae*/ false, $res$$Register);
%}
Expand All @@ -206,7 +206,7 @@ instruct weakCompareAndSwapNAcq_shenandoah(mRegI res, indirect mem, mRegN oldval

ins_encode %{
// Weak is not currently supported by ShenandoahBarrierSet::cmpxchg_oop
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ true, /*is_cae*/ false, $res$$Register);
%}
Expand All @@ -223,7 +223,7 @@ instruct weakCompareAndSwapPAcq_shenandoah(mRegI res, indirect mem, mRegP oldval

ins_encode %{
// Weak is not currently supported by ShenandoahBarrierSet::cmpxchg_oop
Address addr(as_Register($mem$$base), $mem$$disp);
Address addr(as_Register($mem$$base), 0);
ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, addr, $oldval$$Register, $newval$$Register,
/*acquire*/ true, /*is_cae*/ false, $res$$Register);
%}
Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/loongarch/gc/x/x_loongarch_64.ad
View file
Original file line number Diff line number Diff line change
Expand Up @@ -56,12 +56,12 @@ static void x_compare_and_swap(MacroAssembler& _masm, const MachNode* node,
// Weak CAS operations are thus only emitted if the barrier is elided.
Address addr(mem);
if (node->barrier_data() == XLoadBarrierElided) {
__ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* barrier */,
__ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* acquire */,
weak /* weak */, false /* exchange */);
__ move(res, tmp);
} else {
__ move(tmp, oldval);
__ cmpxchg(addr, tmp, newval, AT, true /* retold */, acquire /* barrier */,
__ cmpxchg(addr, tmp, newval, AT, true /* retold */, acquire /* acquire */,
false /* weak */, false /* exchange */);
__ move(res, AT);

Expand All @@ -70,7 +70,7 @@ static void x_compare_and_swap(MacroAssembler& _masm, const MachNode* node,
__ andr(AT, AT, tmp);
__ beqz(AT, good);
x_load_barrier_slow_path(_masm, node, addr, tmp, res /* used as tmp */);
__ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* barrier */, weak /* weak */, false /* exchange */);
__ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* acquire */, weak /* weak */, false /* exchange */);
__ move(res, tmp);
__ bind(good);
}
Expand Down
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