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I2C Resource Optimization #83

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I2C Resource Optimization #83

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3 changes: 3 additions & 0 deletions data/pins_sonata.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -187,3 +187,6 @@ set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS18 } [get_ports ethmac_cs]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

# Force I2C FIFOs to use distributed RAM
set_property RAM_STYLE distributed [get_cells -hierarchical -regexp {u_sonata_system/u_i2c.*/i2c_core/u_fifos/u_ram_1p/u_mem/gen_generic.u_impl_generic/mem_reg}]
3 changes: 2 additions & 1 deletion vendor/lowrisc_ip/ip/i2c/rtl/i2c_core.sv
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Expand Up @@ -200,7 +200,8 @@ module i2c_core import i2c_pkg::*;
assign sda_o = override ? reg2hw.ovrd.sdaval : sda_out_fsm;

assign host_enable = reg2hw.ctrl.enablehost.q;
assign target_enable = reg2hw.ctrl.enabletarget.q;
//assign target_enable = reg2hw.ctrl.enabletarget.q;
assign target_enable = 1'b0;
assign line_loopback = reg2hw.ctrl.llpbk.q;

// Target loopback simply plays back whatever is received from the external host
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