Added pair.ttl

pair.ttl

@@ -0,0 +1,151 @@
+@prefix : <http://odroid.0xFFFFFFFF.in/psoc5lp/ns#> .
+:DSI13  :offset :0x4D00 .
+:DSI12  :offset :0x4C00 . 
+:DSI7   :offset :0x4700 . 
+:DSI6   :offset :0x4600 . 
+:DSI5   :offset :0x4500 . 
+:DSI4   :offset :0x4400 . 
+:B1_P5  :offset :0x1B00 . 
+:B1_P9  :offset :0x1900 . 
+:B0_P4  :offset :0x0900 . 
+:B0_P5  :offset :0x0B00 . 
+:B0_P6  :offset :0x0D00 . 
+:B0_P7  :offset :0x0F00 . 
+:B1_P2  :offset :0x1500 . 
+:B1_P3  :offset :0x1700 . 
+:B0_P3  :offset :0x0700 . 
+:B0_P2  :offset :0x0500 . 
+:B0_P1  :offset :0x0300 . 
+:B0_P0  :offset :0x0100 . 
+:DSI9   :offset :0x4900 . 
+:DSI8   :offset :0x4800 . 
+:DSI3   :offset :0x4300 . 
+:DSI2   :offset :0x4200 . 
+:DSI1   :offset :0x4100 . 
+:DSI0   :offset :0x4000 . 
+
+:DSI13  :checker :B .
+:DSI12  :checker :A . 
+:DSI7   :checker :B . 
+:DSI6   :checker :A . 
+:DSI5   :checker :B . 
+:DSI4   :checker :A . 
+:B1_P5  :checker :A . 
+:B1_P9  :checker :B . 
+:B0_P4  :checker :A . 
+:B0_P5  :checker :B . 
+:B0_P6  :checker :A . 
+:B0_P7  :checker :B . 
+:B1_P2  :checker :B . 
+:B1_P3  :checker :A . 
+:B0_P3  :checker :B . 
+:B0_P2  :checker :A . 
+:B0_P1  :checker :B . 
+:B0_P0  :checker :A . 
+:DSI9   :checker :A . 
+:DSI8   :checker :B . 
+:DSI3   :checker :A . 
+:DSI2   :checker :B . 
+:DSI1   :checker :A . 
+:DSI0   :checker :B . 
+
+:DSI13  :bank 4 .
+:DSI12  :bank 4 . 
+:DSI7   :bank 4 . 
+:DSI6   :bank 4 . 
+:DSI5   :bank 4 . 
+:DSI4   :bank 4 . 
+:B1_P5  :bank 1 . 
+:B1_P9  :bank 1 . 
+:B0_P4  :bank 0 . 
+:B0_P5  :bank 0 . 
+:B0_P6  :bank 0 . 
+:B0_P7  :bank 0 . 
+:B1_P2  :bank 1 . 
+:B1_P3  :bank 1 . 
+:B0_P3  :bank 0 . 
+:B0_P2  :bank 0 . 
+:B0_P1  :bank 0 . 
+:B0_P0  :bank 0 . 
+:DSI9   :bank 4 . 
+:DSI8   :bank 4 . 
+:DSI3   :bank 4 . 
+:DSI2   :bank 4 . 
+:DSI1   :bank 4 . 
+:DSI0   :bank 4 . 
+
+:DSI13  :tile_x 0 .
+:DSI12  :tile_x 1 . 
+:DSI7   :tile_x 2 . 
+:DSI6   :tile_x 3 . 
+:DSI5   :tile_x 4 . 
+:DSI4   :tile_x 5 . 
+:B1_P5  :tile_x 0 . 
+:B1_P9  :tile_x 1 . 
+:B0_P4  :tile_x 2 . 
+:B0_P5  :tile_x 3 . 
+:B0_P6  :tile_x 4 . 
+:B0_P7  :tile_x 5 . 
+:B1_P2  :tile_x 0 . 
+:B1_P3  :tile_x 1 . 
+:B0_P3  :tile_x 2 . 
+:B0_P2  :tile_x 3 . 
+:B0_P1  :tile_x 4 . 
+:B0_P0  :tile_x 5 . 
+:DSI9   :tile_x 0 . 
+:DSI8   :tile_x 1 . 
+:DSI3   :tile_x 2 . 
+:DSI2   :tile_x 3 . 
+:DSI1   :tile_x 4 . 
+:DSI0   :tile_x 5 .
+
+:DSI13  :tile_y 0 .
+:DSI12  :tile_y 0 . 
+:DSI7   :tile_y 0 . 
+:DSI6   :tile_y 0 . 
+:DSI5   :tile_y 0 . 
+:DSI4   :tile_y 0 . 
+:B1_P5  :tile_y 1 . 
+:B1_P9  :tile_y 1 . 
+:B0_P4  :tile_y 1 . 
+:B0_P5  :tile_y 1 . 
+:B0_P6  :tile_y 1 . 
+:B0_P7  :tile_y 1 . 
+:B1_P2  :tile_y 2 . 
+:B1_P3  :tile_y 2 . 
+:B0_P3  :tile_y 2 . 
+:B0_P2  :tile_y 2 . 
+:B0_P1  :tile_y 2 . 
+:B0_P0  :tile_y 2 . 
+:DSI9   :tile_y 3 . 
+:DSI8   :tile_y 3 . 
+:DSI3   :tile_y 3 . 
+:DSI2   :tile_y 3 . 
+:DSI1   :tile_y 3 . 
+:DSI0   :tile_y 3 .
+
+:DSI13  :tile_y 0 .
+:DSI12  :tile_y 0 . 
+:DSI7   :tile_y 0 . 
+:DSI6   :tile_y 0 . 
+:DSI5   :tile_y 0 . 
+:DSI4   :tile_y 0 . 
+:B1_P5  :tile_y 1 . 
+:B1_P9  :tile_y 1 . 
+:B0_P4  :tile_y 1 . 
+:B0_P5  :tile_y 1 . 
+:B0_P6  :tile_y 1 . 
+:B0_P7  :tile_y 1 . 
+:B1_P2  :tile_y 2 . 
+:B1_P3  :tile_y 2 . 
+:B0_P3  :tile_y 2 . 
+:B0_P2  :tile_y 2 . 
+:B0_P1  :tile_y 2 . 
+:B0_P0  :tile_y 2 . 
+:DSI9   :tile_y 3 . 
+:DSI8   :tile_y 3 . 
+:DSI3   :tile_y 3 . 
+:DSI2   :tile_y 3 . 
+:DSI1   :tile_y 3 . 
+:DSI0   :tile_y 3 .
+