sayma: drive filtered_clk_sel on master variant

m-labs · Feb 6, 2020 · 6d26def · 6d26def
1 parent 52ec849
commit 6d26def
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
@@ -388,6 +388,7 @@ def __init__(self, **kwargs):
         self.config["SI5324_AS_SYNTHESIZER"] = None
         self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
 
+        self.comb += platform.request("filtered_clk_sel").eq(1)
         self.comb += platform.request("sfp_tx_disable", 0).eq(0)
         self.submodules.drtio_transceiver = gth_ultrascale.GTH(
             clock_pads=platform.request("cdr_clk_clean", 0),